From abe3a7da04a3703bd504b5ed2e13ecc79dff4bd0 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Wed, 2 Nov 2022 23:48:21 -0600
Subject: Add bus master forward signals: irq, cpu_clk

---
 rtl/top/conspiracion.sv | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

(limited to 'rtl/top')

diff --git a/rtl/top/conspiracion.sv b/rtl/top/conspiracion.sv
index 940e46a..41b614f 100644
--- a/rtl/top/conspiracion.sv
+++ b/rtl/top/conspiracion.sv
@@ -35,7 +35,7 @@ module conspiracion
 
 	logic[29:0] addr;
 	logic[31:0] data_rd, data_wr;
-	logic clk_core, ready, write, start;
+	logic cpu_clk, ready, write, start, irq;
 
 	arm810 core
 	(
@@ -53,12 +53,14 @@ module conspiracion
 
 	platform plat
 	(
+		.master_0_core_cpu_clk(cpu_clk),
 		.master_0_core_addr(addr),
 		.master_0_core_data_rd(data_rd),
 		.master_0_core_data_wr(data_wr),
 		.master_0_core_ready(ready),
 		.master_0_core_write(write),
 		.master_0_core_start(start),
+		.master_0_core_irq(irq),
 		.pll_0_outclk3_clk(),
 		.pio_0_external_connection_export(),
 		.*
-- 
cgit v1.2.3