From 583a1ebaafe285c223afbfcc60bb68e6c10174ca Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Tue, 27 Sep 2022 15:13:10 -0600 Subject: Add simple loop execution testbench --- rtl/top/conspiracion.sv | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'rtl/top') diff --git a/rtl/top/conspiracion.sv b/rtl/top/conspiracion.sv index 79e8bb8..50b9cd8 100644 --- a/rtl/top/conspiracion.sv +++ b/rtl/top/conspiracion.sv @@ -16,11 +16,7 @@ module conspiracion inout wire memory_mem_dqs_n, output wire memory_mem_odt, output wire memory_mem_dm, - input wire memory_oct_rzqin, - - input logic dir, clr, mov, add, io, - output logic[7:0] out, - output logic done + input wire memory_oct_rzqin ); //TODO -- cgit v1.2.3