From f3b18ead59ae02f95dabbf0a1dea40873a816975 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Sun, 21 Jan 2024 06:23:46 -0600
Subject: rtl: refactor filenames and directory hierarchy

---
 rtl/smp/pe.sv     | 53 -----------------------------------------------------
 rtl/smp/smp_pe.sv | 53 +++++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 53 insertions(+), 53 deletions(-)
 delete mode 100644 rtl/smp/pe.sv
 create mode 100644 rtl/smp/smp_pe.sv

(limited to 'rtl/smp')

diff --git a/rtl/smp/pe.sv b/rtl/smp/pe.sv
deleted file mode 100644
index 5c675ee..0000000
--- a/rtl/smp/pe.sv
+++ /dev/null
@@ -1,53 +0,0 @@
-module smp_pe
-#(parameter IS_BSP=0)
-(
-	input  logic	  clk,
-	                  rst_n,
-	
-	input  logic      write,
-	input  logic[7:0] writedata,
-	output logic[7:0] readdata,
-
-	input  logic      cpu_alive,
-	                  cpu_halted,
-	                  breakpoint,
-
-	output logic      halt,
-	                  step
-);
-
-	struct packed
-	{
-		logic step, halt, run;
-	} req;
-
-	struct packed
-	{
-		logic alive, breakpoint, cpu_halted;
-	} status, status_out;
-
-	assign req = writedata[$bits(req) - 1:0];
-	assign readdata = {{(8 - $bits(status_out)){1'b0}}, status_out};
-
-	always_comb begin
-		status_out = status;
-		status_out.alive = cpu_alive;
-	end
-
-	always @(posedge clk or negedge rst_n)
-		if (!rst_n) begin
-			halt <= IS_BSP ? 0 : 1; // Boot es single-core
-			step <= 0;
-			status <= {($bits(status)){1'b0}};
-		end else begin
-			status.breakpoint <= breakpoint;
-			status.cpu_halted <= cpu_halted;
-
-			//Se hace halt hasta el siguiente ciclo después de que se 
-			//solicita el breakpoint
-			step <= (step && !breakpoint) || (req.step && write);
-			halt <= (halt || breakpoint || (req.halt && write))
-			     && !((req.run || req.step) && write);
-		end
-
-endmodule
diff --git a/rtl/smp/smp_pe.sv b/rtl/smp/smp_pe.sv
new file mode 100644
index 0000000..5c675ee
--- /dev/null
+++ b/rtl/smp/smp_pe.sv
@@ -0,0 +1,53 @@
+module smp_pe
+#(parameter IS_BSP=0)
+(
+	input  logic	  clk,
+	                  rst_n,
+	
+	input  logic      write,
+	input  logic[7:0] writedata,
+	output logic[7:0] readdata,
+
+	input  logic      cpu_alive,
+	                  cpu_halted,
+	                  breakpoint,
+
+	output logic      halt,
+	                  step
+);
+
+	struct packed
+	{
+		logic step, halt, run;
+	} req;
+
+	struct packed
+	{
+		logic alive, breakpoint, cpu_halted;
+	} status, status_out;
+
+	assign req = writedata[$bits(req) - 1:0];
+	assign readdata = {{(8 - $bits(status_out)){1'b0}}, status_out};
+
+	always_comb begin
+		status_out = status;
+		status_out.alive = cpu_alive;
+	end
+
+	always @(posedge clk or negedge rst_n)
+		if (!rst_n) begin
+			halt <= IS_BSP ? 0 : 1; // Boot es single-core
+			step <= 0;
+			status <= {($bits(status)){1'b0}};
+		end else begin
+			status.breakpoint <= breakpoint;
+			status.cpu_halted <= cpu_halted;
+
+			//Se hace halt hasta el siguiente ciclo después de que se 
+			//solicita el breakpoint
+			step <= (step && !breakpoint) || (req.step && write);
+			halt <= (halt || breakpoint || (req.halt && write))
+			     && !((req.run || req.step) && write);
+		end
+
+endmodule
-- 
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