From 7baed021cdf61891bc9454050edf7f2a0f75b45b Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Fri, 27 Oct 2023 05:55:35 -0600
Subject: rtl/gfx: implement fp16 on verilator

---
 rtl/gfx/fp_add.sv | 17 +++++++++++++++++
 rtl/gfx/fp_mul.sv | 17 +++++++++++++++++
 2 files changed, 34 insertions(+)

(limited to 'rtl/gfx')

diff --git a/rtl/gfx/fp_add.sv b/rtl/gfx/fp_add.sv
index fad4768..e8e0c5f 100644
--- a/rtl/gfx/fp_add.sv
+++ b/rtl/gfx/fp_add.sv
@@ -18,6 +18,23 @@ module fp_add
 		.areset(0),
 		.*
 	);
+`else
+	fp a_pipeline[`FP_ADD_STAGES - 1], b_pipeline[`FP_ADD_STAGES - 1];
+
+	integer i;
+
+	always @(posedge clk)
+		if (!stall) begin
+			a_pipeline[0] <= a;
+			b_pipeline[0] <= b;
+
+			for (i = 1; i < `FP_ADD_STAGES - 1; ++i) begin
+				a_pipeline[i] <= a_pipeline[i - 1];
+				b_pipeline[i] <= b_pipeline[i - 1];
+			end
+
+			q <= $c("taller::fp_add(", a_pipeline[`FP_ADD_STAGES - 2], ", ", b_pipeline[`FP_ADD_STAGES - 2], ")");
+		end
 `endif
 
 endmodule
diff --git a/rtl/gfx/fp_mul.sv b/rtl/gfx/fp_mul.sv
index 90d30fb..af5e09c 100644
--- a/rtl/gfx/fp_mul.sv
+++ b/rtl/gfx/fp_mul.sv
@@ -18,6 +18,23 @@ module fp_mul
 		.areset(0),
 		.*
 	);
+`else
+	fp a_pipeline[`FP_MUL_STAGES - 1], b_pipeline[`FP_MUL_STAGES - 1];
+
+	integer i;
+
+	always @(posedge clk)
+		if (!stall) begin
+			a_pipeline[0] <= a;
+			b_pipeline[0] <= b;
+
+			for (i = 1; i < `FP_MUL_STAGES - 1; ++i) begin
+				a_pipeline[i] <= a_pipeline[i - 1];
+				b_pipeline[i] <= b_pipeline[i - 1];
+			end
+
+			q <= $c("taller::fp_mul(", a_pipeline[`FP_MUL_STAGES - 2], ", ", b_pipeline[`FP_MUL_STAGES - 2], ")");
+		end
 `endif
 
 endmodule
-- 
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