From c1c1f1e823099c82d02e94827a64d7a0b223048e Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Sun, 22 Oct 2023 00:16:40 -0600
Subject: rtl/gfx: reimplement multiplier as a much smaller mat-vec pipeline

---
 rtl/gfx/pipeline_flow.sv | 40 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)
 create mode 100644 rtl/gfx/pipeline_flow.sv

(limited to 'rtl/gfx/pipeline_flow.sv')

diff --git a/rtl/gfx/pipeline_flow.sv b/rtl/gfx/pipeline_flow.sv
new file mode 100644
index 0000000..2b9c891
--- /dev/null
+++ b/rtl/gfx/pipeline_flow.sv
@@ -0,0 +1,40 @@
+`include "gfx/gfx_defs.sv"
+
+module pipeline_flow
+#(parameter STAGES=0)
+(
+	input  logic clk,
+	             rst_n,
+
+	input  logic in_valid,
+	             out_ready,
+
+	output logic in_ready,
+	             out_valid,
+	             stall
+);
+
+	logic valid[STAGES];
+
+	assign stall = !in_ready;
+	assign in_ready = out_ready || !out_valid;
+	assign out_valid = valid[STAGES - 1];
+
+	always_ff @(posedge clk or negedge rst_n)
+		if (!rst_n)
+			valid[0] <= 0;
+		else if (in_ready)
+			valid[0] <= in_valid;
+
+	genvar i;
+	generate
+		for (i = 1; i < STAGES; ++i) begin: pipeline
+			always_ff @(posedge clk or negedge rst_n)
+				if (!rst_n)
+					valid[i] <= 0;
+				else if (in_ready)
+					valid[i] <= valid[i - 1];
+		end
+	endgenerate
+
+endmodule
-- 
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