From d076c33ffb6e3c0d96ee6b5dce0fcf48be8d3582 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Tue, 21 Nov 2023 14:39:05 -0600 Subject: rtl/gfx: implement SP register files --- rtl/gfx/gfx_sp_regs.sv | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 rtl/gfx/gfx_sp_regs.sv (limited to 'rtl/gfx/gfx_sp_regs.sv') diff --git a/rtl/gfx/gfx_sp_regs.sv b/rtl/gfx/gfx_sp_regs.sv new file mode 100644 index 0000000..68aaf06 --- /dev/null +++ b/rtl/gfx/gfx_sp_regs.sv @@ -0,0 +1,39 @@ +`include "gfx/gfx_defs.sv" + +module gfx_sp_regs +( + input logic clk, + + input vreg_num rd_a_reg, + output mat4 rd_a_data, + + input vreg_num rd_b_reg, + output mat4 rd_b_data, + + input logic wr, + input vreg_num wr_reg, + input mat4 wr_data +); + + genvar i; + generate + for (i = 0; i < `GFX_SP_LANES; ++i) begin: lanes + gfx_sp_file a + ( + .rd_reg(rd_a_reg), + .rd_data(rd_a_data[i]), + .wr_data(wr_data[i]), + .* + ); + + gfx_sp_file b + ( + .rd_reg(rd_b_reg), + .rd_data(rd_b_data[i]), + .wr_data(wr_data[i]), + .* + ); + end + endgenerate + +endmodule -- cgit v1.2.3