From d076c33ffb6e3c0d96ee6b5dce0fcf48be8d3582 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Tue, 21 Nov 2023 14:39:05 -0600
Subject: rtl/gfx: implement SP register files

---
 rtl/gfx/gfx_sp_file.sv | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)
 create mode 100644 rtl/gfx/gfx_sp_file.sv

(limited to 'rtl/gfx/gfx_sp_file.sv')

diff --git a/rtl/gfx/gfx_sp_file.sv b/rtl/gfx/gfx_sp_file.sv
new file mode 100644
index 0000000..5dced6e
--- /dev/null
+++ b/rtl/gfx/gfx_sp_file.sv
@@ -0,0 +1,32 @@
+`include "gfx/gfx_defs.sv"
+
+module gfx_sp_file
+(
+	input  logic    clk,
+
+	input  vreg_num rd_reg,
+	output vec4     rd_data,
+
+	input  logic    wr,
+	input  vreg_num wr_reg,
+	input  vec4     wr_data
+);
+
+	vec4 file[1 << $bits(vreg_num)], hold_rd_data, hold_wr_data;
+	logic hold_wr;
+	vreg_num hold_rd_reg, hold_wr_reg;
+
+	always_ff @(posedge clk) begin
+		hold_wr <= wr;
+		hold_wr_reg <= wr_reg;
+		hold_wr_data <= wr_data;
+
+		rd_data <= hold_rd_data;
+		hold_rd_reg <= rd_reg;
+		hold_rd_data <= file[hold_rd_reg];
+
+		if (hold_wr)
+			file[hold_wr_reg] <= hold_wr_data;
+	end
+
+endmodule
-- 
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