From b21c321a059e11edeece1c90d97776bb0716d7a0 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Thu, 16 May 2024 01:08:04 -0600
Subject: rtl: fix quartus errors: parser, synthesis, fitter

---
 rtl/gfx/gfx_isa.sv | 132 ++++++++++++++++++++++++++++-------------------------
 1 file changed, 69 insertions(+), 63 deletions(-)

(limited to 'rtl/gfx/gfx_isa.sv')

diff --git a/rtl/gfx/gfx_isa.sv b/rtl/gfx/gfx_isa.sv
index 7239478..cc34156 100644
--- a/rtl/gfx/gfx_isa.sv
+++ b/rtl/gfx/gfx_isa.sv
@@ -5,80 +5,86 @@ package gfx_isa;
 
 	typedef logic signed[7:0] pc_offset;
 
-	typedef union packed
+	typedef struct packed
 	{
 		sgpr_num sgpr;
-
-		struct packed
-		{
-			logic[$bits(sgpr_num) - $bits(vgpr_num) - 1:0] reserved;
-			vgpr_num                                       num;
-		} vgpr;
-	} xgpr_num;
+	} xgpr_sgpr;
 
 	typedef struct packed
 	{
-		enum logic[1:0]
-		{
-			REGS_SVS = 2'b00,
-			REGS_SSS = 2'b01,
-			REGS_VVS = 2'b10,
-			REGS_VVV = 2'b11
-		} reg_mode;
+		logic[$bits(sgpr_num) - $bits(vgpr_num) - 1:0] reserved;
+		vgpr_num                                       vgpr;
+	} xgpr_vgpr;
 
-		union packed
-		{
-			struct packed
-			{
-				logic b_is_imm;
+	typedef xgpr_vgpr xgpr_num;
 
-				union packed
-				{
-					logic[12:0] imm;
+	typedef enum logic[1:0]
+	{
+		REGS_SVS = 2'b00,
+		REGS_SSS = 2'b01,
+		REGS_VVS = 2'b10,
+		REGS_VVV = 2'b11
+	} xgpr_mode;
 
-					struct packed
-					{
-						logic      from_consts;
-						logic[7:0] reserved;
-						xgpr_num   r;
-					} read;
-				} b;
+	typedef struct packed
+	{
+		logic[12:0] imm;
+	} dst_src_rr_b_imm;
 
-				xgpr_num ra,
-				         rd;
-			} rr;
-		} dst_src;
+	typedef struct packed
+	{
+		logic      from_consts;
+		logic[7:0] reserved;
+		xgpr_num   r;
+	} dst_src_rr_b_read;
 
-		logic reg_rev;
+	typedef struct packed
+	{
+		logic             b_is_imm;
+		dst_src_rr_b_read b;
+		xgpr_num          ra,
+		                  rd;
+	} dst_src_rr;
 
-		union packed
-		{
-			struct packed
-			{
-				enum logic[4:0]
-				{
-					INSN_FPINT_MOV  = 0,
-					INSN_FPINT_FMUL = 1,
-					INSN_FPINT_IMUL = 2,
-					INSN_FPINT_FADD = 3,
-					INSN_FPINT_RES4 = 4,
-					INSN_FPINT_FMAX = 5,
-					INSN_FPINT_RES6 = 6,
-					INSN_FPINT_FMIN = 7,
-					INSN_FPINT_RES8 = 8,
-					INSN_FPINT_FCVT = 9,
-					INSN_FPINT_RES[10:31]
-				} op;
-			} fpint;
-		} by_class;
+	typedef enum logic[1:0]
+	{
+		INSN_FPINT = 2'd0,
+		INSN_MEM   = 2'd1,
+		INSN_SFU   = 2'd2,
+		INSN_GROUP = 2'd3
+	} insn_class;
+
+	typedef enum logic[4:0]
+	{
+		INSN_FPINT_MOV  = 5'd0,
+		INSN_FPINT_FMUL = 5'd1,
+		INSN_FPINT_IMUL = 5'd2,
+		INSN_FPINT_FADD = 5'd3,
+		INSN_FPINT_RES4 = 5'd4,
+		INSN_FPINT_FMAX = 5'd5,
+		INSN_FPINT_RES6 = 5'd6,
+		INSN_FPINT_FMIN = 5'd7,
+		INSN_FPINT_RES8 = 5'd8,
+		INSN_FPINT_FCVT = 5'd9,
+		INSN_FPINT_RES[10:31]
+	} insn_fpint_op;
+
+	typedef struct packed
+	{
+		xgpr_mode     reg_mode;
+		dst_src_rr    dst_src;
+		logic         reg_rev;
+		insn_fpint_op op;
+		insn_class    op_class;
+	} insn_fpint;
 
-		enum logic[1:0]
-		{
-			INSN_FPINT = 0,
-			INSN_MEM   = 1,
-			INSN_SFU   = 2,
-			INSN_GROUP = 3
-		} insn_class;
-	} insn_word;
+	typedef struct packed
+	{
+		xgpr_mode   reg_mode;
+		dst_src_rr  dst_src;
+		logic       reg_rev;
+		logic[4:0]  op_data;
+		insn_class  op_class;
+	} insn_any;
 
 endpackage
-- 
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