From d5de20fade70a0d454e3aa0087313ca715ff8759 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Thu, 2 Nov 2023 22:19:26 -0600
Subject: rtl/gfx: rename modules

---
 rtl/gfx/gfx_fp_add.sv | 40 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)
 create mode 100644 rtl/gfx/gfx_fp_add.sv

(limited to 'rtl/gfx/gfx_fp_add.sv')

diff --git a/rtl/gfx/gfx_fp_add.sv b/rtl/gfx/gfx_fp_add.sv
new file mode 100644
index 0000000..6ba7b1c
--- /dev/null
+++ b/rtl/gfx/gfx_fp_add.sv
@@ -0,0 +1,40 @@
+`include "gfx/gfx_defs.sv"
+
+module gfx_fp_add
+(
+	input  logic clk,
+
+	input  fp    a,
+	             b,
+	input  logic stall,
+
+	output fp    q
+);
+
+`ifndef VERILATOR
+	ip_fp_add ip_add
+	(
+		.en(!stall),
+		.areset(0),
+		.*
+	);
+`else
+	fp a_pipeline[`FP_ADD_STAGES - 1], b_pipeline[`FP_ADD_STAGES - 1];
+
+	integer i;
+
+	always_ff @(posedge clk)
+		if (!stall) begin
+			a_pipeline[0] <= a;
+			b_pipeline[0] <= b;
+
+			for (i = 1; i < `FP_ADD_STAGES - 1; ++i) begin
+				a_pipeline[i] <= a_pipeline[i - 1];
+				b_pipeline[i] <= b_pipeline[i - 1];
+			end
+
+			q <= $c("taller::fp_add(", a_pipeline[`FP_ADD_STAGES - 2], ", ", b_pipeline[`FP_ADD_STAGES - 2], ")");
+		end
+`endif
+
+endmodule
-- 
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