From c1c1f1e823099c82d02e94827a64d7a0b223048e Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Sun, 22 Oct 2023 00:16:40 -0600
Subject: rtl/gfx: reimplement multiplier as a much smaller mat-vec pipeline

---
 rtl/gfx/fp_add.sv | 11 ++---------
 1 file changed, 2 insertions(+), 9 deletions(-)

(limited to 'rtl/gfx/fp_add.sv')

diff --git a/rtl/gfx/fp_add.sv b/rtl/gfx/fp_add.sv
index 6cf4874..fad4768 100644
--- a/rtl/gfx/fp_add.sv
+++ b/rtl/gfx/fp_add.sv
@@ -3,25 +3,18 @@
 module fp_add
 (
 	input  logic clk,
-	             rst_n,
 
-	input  logic start,
 	input  fp    a,
 	             b,
+	input  logic stall,
 
-	output logic done,
 	output fp    q
 );
 
-	pipelined_flow #(.STAGES(`FP_ADD_STAGES)) stages
-	(
-		.*
-	);
-
 `ifndef VERILATOR
 	ip_fp_add ip_add
 	(
-		.en(1),
+		.en(!stall),
 		.areset(0),
 		.*
 	);
-- 
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