From e794cecaa4779ed884589a67f6cba3cd712e4b14 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Mon, 31 Oct 2022 14:15:30 -0600
Subject: Display undefined instruction messages in simulation

---
 rtl/core/control/control.sv | 9 +++++++++
 1 file changed, 9 insertions(+)

(limited to 'rtl/core')

diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv
index 059cb2d..c1ac5a1 100644
--- a/rtl/core/control/control.sv
+++ b/rtl/core/control/control.sv
@@ -19,6 +19,10 @@ module core_control
 	                       mem_ready,
 	input  word            mem_data_rd,
 
+`ifdef VERILATOR
+	input  word            insn,
+`endif
+
 	output logic           stall,
 	                       branch,
 	                       writeback,
@@ -154,6 +158,11 @@ module core_control
 				writeback <= final_writeback;
 				undefined <= dec.undefined;
 
+`ifdef VERILATOR
+				if(dec.undefined)
+					$display("[core] undefined insn: [0x%08x] %08x", fetch_insn_pc << 2, insn);
+`endif
+
 				rd <= final_rd;
 				pc <= fetch_insn_pc;
 				pc_visible <= next_pc_visible;
-- 
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