From bc98bc905c2e796f0d587719196f7e4bf344510a Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Fri, 29 Sep 2023 19:50:01 -0600
Subject: platform: add CPUs and caches to qsys

---
 rtl/core/cp15/cache.sv     | 15 ---------------
 rtl/core/cp15/cache_ops.sv | 15 +++++++++++++++
 2 files changed, 15 insertions(+), 15 deletions(-)
 delete mode 100644 rtl/core/cp15/cache.sv
 create mode 100644 rtl/core/cp15/cache_ops.sv

(limited to 'rtl/core')

diff --git a/rtl/core/cp15/cache.sv b/rtl/core/cp15/cache.sv
deleted file mode 100644
index cb6d4ad..0000000
--- a/rtl/core/cp15/cache.sv
+++ /dev/null
@@ -1,15 +0,0 @@
-`include "core/uarch.sv"
-
-module core_cp15_cache
-(
-	input  logic     clk,
-	                 rst_n,
-
-	input  logic     load,
-	                 transfer,
-	input  word      write
-);
-
-	//TODO
-
-endmodule
diff --git a/rtl/core/cp15/cache_ops.sv b/rtl/core/cp15/cache_ops.sv
new file mode 100644
index 0000000..cb6d4ad
--- /dev/null
+++ b/rtl/core/cp15/cache_ops.sv
@@ -0,0 +1,15 @@
+`include "core/uarch.sv"
+
+module core_cp15_cache
+(
+	input  logic     clk,
+	                 rst_n,
+
+	input  logic     load,
+	                 transfer,
+	input  word      write
+);
+
+	//TODO
+
+endmodule
-- 
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