From acca3eb31a051f335c51306786bb972c21634998 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Thu, 10 Nov 2022 10:11:33 -0600 Subject: Fix reset glitches --- rtl/core/arm810.sv | 4 ++++ rtl/core/control/data.sv | 5 +++-- rtl/core/control/ldst/ldst.sv | 2 +- rtl/core/control/writeback.sv | 2 +- rtl/core/decode/ldst/addr.sv | 1 + rtl/core/decode/mux.sv | 10 +++++++--- rtl/core/mmu/mmu.sv | 4 ++-- rtl/core/regs/file.sv | 1 + 8 files changed, 20 insertions(+), 9 deletions(-) (limited to 'rtl/core') diff --git a/rtl/core/arm810.sv b/rtl/core/arm810.sv index 083163d..9b36a41 100644 --- a/rtl/core/arm810.sv +++ b/rtl/core/arm810.sv @@ -80,6 +80,10 @@ module arm810 psr_flags flags; psr_intmask intmask; + //TODO + assign psr_write = 0; + assign psr_saved = 0; + core_psr psr ( .mask(intmask), diff --git a/rtl/core/control/data.sv b/rtl/core/control/data.sv index fc936dc..0824eac 100644 --- a/rtl/core/control/data.sv +++ b/rtl/core/control/data.sv @@ -69,6 +69,7 @@ module core_control_data c_in <= 0; shifter <= {$bits(shifter){1'b0}}; data_imm <= {$bits(data_imm){1'b0}}; + saved_base <= 0; data_shift_imm <= {$bits(data_shift_imm){1'b0}}; data_snd_is_imm <= 0; data_snd_shift_by_reg <= 0; @@ -77,10 +78,10 @@ module core_control_data alu <= dec.data.op; c_in <= flags.c; - data_snd_is_imm <= dec.snd.is_imm; - data_snd_shift_by_reg <= dec.snd.shift_by_reg; data_imm <= dec.snd.imm; data_shift_imm <= dec.snd.shift_imm; + data_snd_is_imm <= dec.snd.is_imm; + data_snd_shift_by_reg <= dec.snd.shift_by_reg; shifter.shr <= dec.snd.shr; shifter.ror <= dec.snd.ror; diff --git a/rtl/core/control/ldst/ldst.sv b/rtl/core/control/ldst/ldst.sv index baf0054..ef91775 100644 --- a/rtl/core/control/ldst/ldst.sv +++ b/rtl/core/control/ldst/ldst.sv @@ -52,9 +52,9 @@ module core_control_ldst ldst_increment <= 0; mem_addr <= {$bits(mem_addr){1'b0}}; + mem_regs <= {$bits(mem_regs){1'b0}}; mem_write <= 0; mem_start <= 0; - mem_regs <= {$bits(mem_regs){1'b0}}; mem_offset <= 0; end else unique case(next_cycle) ISSUE: begin diff --git a/rtl/core/control/writeback.sv b/rtl/core/control/writeback.sv index 1fb3ced..74eb47c 100644 --- a/rtl/core/control/writeback.sv +++ b/rtl/core/control/writeback.sv @@ -144,7 +144,7 @@ module core_control_writeback update_flags <= final_update_flags; EXCEPTION: - final_update_flags <= 0; + update_flags <= 0; endcase unique case(next_cycle) diff --git a/rtl/core/decode/ldst/addr.sv b/rtl/core/decode/ldst/addr.sv index 4a61231..345f0ea 100644 --- a/rtl/core/decode/ldst/addr.sv +++ b/rtl/core/decode/ldst/addr.sv @@ -10,5 +10,6 @@ module core_decode_ldst_addr assign alu.op = ldst.increment ? `ALU_ADD : `ALU_SUB; assign alu.rn = ldst.rn; assign alu.rd = ldst.rd; + assign alu.uses_rn = 1; endmodule diff --git a/rtl/core/decode/mux.sv b/rtl/core/decode/mux.sv index ebcc098..594b7f0 100644 --- a/rtl/core/decode/mux.sv +++ b/rtl/core/decode/mux.sv @@ -94,13 +94,15 @@ module core_decode_mux snd_ror_if_imm = 1'bx; snd_shift_by_reg_if_reg = 1'bx; - ldst_addr = {($bits(ldst_addr)){1'bx}}; dec_ldst = {($bits(dec_ldst)){1'bx}}; + ldst_addr = {($bits(ldst_addr)){1'bx}}; // El orden de los casos es importante, NO CAMBIAR priority casez(insn `FIELD_OP) `GROUP_B: begin branch = 1; + dec_data.uses_rn = branch_link; + if(branch_link) begin dec_data.op = `ALU_SUB; dec_data.rd = `R14; @@ -186,14 +188,16 @@ module core_decode_mux end `INSN_MRS: begin - dec_snd.is_imm = 0; - dec_snd.r = mrs_rd; + dec_data.rd = mrs_rd; + dec_data.uses_rn = 0; writeback = 1; conditional = 1; end `GROUP_MSR: begin + dec_data.uses_rn = 0; + snd_is_imm = msr_is_imm; snd_ror_if_imm = 1; snd_shift_by_reg_if_reg = 0; diff --git a/rtl/core/mmu/mmu.sv b/rtl/core/mmu/mmu.sv index 185fb6b..cfb223f 100644 --- a/rtl/core/mmu/mmu.sv +++ b/rtl/core/mmu/mmu.sv @@ -97,15 +97,15 @@ module core_mmu if(hold_free) unique case(next_master) INSN: begin - hold_start <= data_start; hold_addr <= data_addr; + hold_start <= data_start; hold_write <= data_write; hold_data_wr <= data_data_wr; end DATA: begin - hold_start <= insn_start; hold_addr <= insn_addr; + hold_start <= insn_start; hold_write <= 0; end endcase diff --git a/rtl/core/regs/file.sv b/rtl/core/regs/file.sv index d9ac251..2ba95e8 100644 --- a/rtl/core/regs/file.sv +++ b/rtl/core/regs/file.sv @@ -36,6 +36,7 @@ module core_reg_file always_ff @(posedge clk or negedge rst_n) if(!rst_n) begin forward <= 0; + rd_actual <= 0; hold_rd_pc <= 0; end else begin forward <= wr_enable && rd_index == wr_index; -- cgit v1.2.3