From 827c40829903d5b870f47ab2f389792ed10211bd Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Tue, 13 Feb 2024 12:14:31 -0600
Subject: rtl/core/control: don't shift branch history registers inside loops

---
 rtl/core/core_control_issue.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'rtl/core')

diff --git a/rtl/core/core_control_issue.sv b/rtl/core/core_control_issue.sv
index 5bd03e1..606d0b8 100644
--- a/rtl/core/core_control_issue.sv
+++ b/rtl/core/core_control_issue.sv
@@ -68,7 +68,7 @@ module core_control_issue
 			pc_visible <= next_pc_visible;
 
 `ifdef VERILATOR
-			if(insn_pc != pc && insn_pc != pc + 1) begin
+			if(insn_pc != pc && insn_pc != pc + 1 && bh0 != {pc, 2'b00}) begin
 				bh0 <= {pc, 2'b00};
 				bh1 <= bh0;
 				bh2 <= bh1;
-- 
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