From d463acba5f9589085afb3dcc4058d82908ff90f2 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Sun, 13 Nov 2022 05:22:23 -0600
Subject: Convert core state machines to Quartus-inferring RTL

---
 rtl/core/uarch.sv | 23 ++++++++++++-----------
 1 file changed, 12 insertions(+), 11 deletions(-)

(limited to 'rtl/core/uarch.sv')

diff --git a/rtl/core/uarch.sv b/rtl/core/uarch.sv
index 5b88559..d553104 100644
--- a/rtl/core/uarch.sv
+++ b/rtl/core/uarch.sv
@@ -124,7 +124,7 @@ typedef struct packed
 	logic[5:0]  shift_imm;
 } snd_decode;
 
-typedef enum
+typedef enum int unsigned
 {
 	LDST_WORD,
 	LDST_BYTE,
@@ -181,17 +181,18 @@ typedef struct packed
 	coproc_decode coproc;
 } insn_decode;
 
-typedef enum
+// Ver comentario en cycles.sv, este diseño es más óptimo
+typedef struct packed
 {
-	ISSUE,
-	RD_INDIRECT_SHIFT,
-	WITH_SHIFT,
-	TRANSFER,
-	BASE_WRITEBACK,
-	EXCEPTION,
-	MUL,
-	MUL_ACC_LD,
-	MUL_HI_WB
+	logic issue,
+	      rd_indirect_shift,
+	      with_shift,
+	      transfer,
+	      base_writeback,
+	      exception,
+	      mul,
+	      mul_acc_ld,
+	      mul_hi_wb;
 } ctrl_cycle;
 
 typedef struct packed
-- 
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