From b328dee91da704474509054043740128e5969c8b Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Mon, 17 Oct 2022 01:14:56 -0600
Subject: Use negative clock edge for register file in Verilator builds

---
 rtl/core/regs/file.sv | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'rtl/core/regs')

diff --git a/rtl/core/regs/file.sv b/rtl/core/regs/file.sv
index 7109edf..e0f9b4c 100644
--- a/rtl/core/regs/file.sv
+++ b/rtl/core/regs/file.sv
@@ -14,7 +14,12 @@ module core_reg_file
 	// Ver comentario en uarch.sv
 	word file[30] /*verilator public*/;
 
+	//FIXME: Esto claramente no sirve
+`ifdef VERILATOR
+	always_ff @(negedge clk) begin
+`else
 	always_ff @(posedge clk) begin
+`endif
 		if(wr_enable)
 			file[wr_index] <= wr_value;
 
-- 
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