From acca3eb31a051f335c51306786bb972c21634998 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Thu, 10 Nov 2022 10:11:33 -0600
Subject: Fix reset glitches

---
 rtl/core/regs/file.sv | 1 +
 1 file changed, 1 insertion(+)

(limited to 'rtl/core/regs')

diff --git a/rtl/core/regs/file.sv b/rtl/core/regs/file.sv
index d9ac251..2ba95e8 100644
--- a/rtl/core/regs/file.sv
+++ b/rtl/core/regs/file.sv
@@ -36,6 +36,7 @@ module core_reg_file
 	always_ff @(posedge clk or negedge rst_n)
 		if(!rst_n) begin
 			forward <= 0;
+			rd_actual <= 0;
 			hold_rd_pc <= 0;
 		end else begin
 			forward <= wr_enable && rd_index == wr_index;
-- 
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