From ec7649eef16c7f9c3ca4b74a1cea95eb2f524b29 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Tue, 27 Sep 2022 15:16:07 -0600 Subject: Fix branching bugs --- rtl/core/regs/regs.sv | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'rtl/core/regs/regs.sv') diff --git a/rtl/core/regs/regs.sv b/rtl/core/regs/regs.sv index 182b240..247c120 100644 --- a/rtl/core/regs/regs.sv +++ b/rtl/core/regs/regs.sv @@ -30,6 +30,7 @@ module core_regs assign pc_word = {pc_visible, 2'b00}; assign rd_value_a = rd_pc_a ? pc_word : file_rd_value_a; assign rd_value_b = rd_pc_b ? pc_word : file_rd_value_b; + assign file_wr_enable = wr_enable & ~wr_pc; assign branch = wr_enable & wr_pc; core_reg_file a @@ -44,7 +45,7 @@ module core_regs ( .rd_index(rd_index_b), .rd_value(file_rd_value_b), - .wr_enable(wr_enable & ~wr_pc), + .wr_enable(file_wr_enable), .* ); -- cgit v1.2.3