From 5d798386c3b1c1dc45a2fbc382c9367ccc27c524 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Wed, 9 Nov 2022 09:25:48 -0600 Subject: Implement reset --- rtl/core/regs/regs.sv | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) (limited to 'rtl/core/regs/regs.sv') diff --git a/rtl/core/regs/regs.sv b/rtl/core/regs/regs.sv index 9cf7033..f9cecad 100644 --- a/rtl/core/regs/regs.sv +++ b/rtl/core/regs/regs.sv @@ -3,6 +3,8 @@ module core_regs ( input logic clk, + rst_n, + input reg_num rd_r_a, rd_r_b, wr_r, @@ -53,16 +55,15 @@ module core_regs .index(wr_index) ); - always_ff @(posedge clk) begin - if(wr_enable) - wr_current <= wr_value; - - branch <= wr_enable && wr_pc; - end + always_ff @(posedge clk or negedge rst_n) + if(!rst_n) begin + branch <= 0; + wr_current <= 0; + end else begin + if(wr_enable) + wr_current <= wr_value; - initial begin - branch = 0; - wr_current = 0; - end + branch <= wr_enable && wr_pc; + end endmodule -- cgit v1.2.3