From 5dc62fde35731279e5ef4c7b334cb97d4f24f656 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Sun, 25 Sep 2022 15:00:25 -0600 Subject: Implement register file --- rtl/core/regs/map.sv | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 rtl/core/regs/map.sv (limited to 'rtl/core/regs/map.sv') diff --git a/rtl/core/regs/map.sv b/rtl/core/regs/map.sv new file mode 100644 index 0000000..b4da988 --- /dev/null +++ b/rtl/core/regs/map.sv @@ -0,0 +1,32 @@ +`include "core/isa.sv" +`include "core/psr.sv" +`include "core/uarch.sv" + +module core_reg_map +( + input reg_num r, + input psr_mode mode, + output logic is_pc, + output reg_index index +); + + reg_index usr; + assign usr = {1'b0, r}; + + always_comb begin + index = 5'bxxxxx; + is_pc = r == `R15; + + if(~is_pc) + unique case(mode) + `MODE_USR, `MODE_SYS: index = usr; + `MODE_FIQ: index = r >= 8 ? usr + 7 : usr; + `MODE_IRQ: index = r >= 13 ? usr + 9 : usr; + `MODE_UND: index = r >= 13 ? usr + 11 : usr; + `MODE_ABT: index = r >= 13 ? usr + 13 : usr; + `MODE_SVC: index = r >= 13 ? usr + 15 : usr; + default: ; + endcase + end + +endmodule -- cgit v1.2.3