From d2fc80b6d8b4a64efa00c8458ae94f6b44ddf6be Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Tue, 20 Dec 2022 16:16:08 -0600
Subject: Fix clock/reset timing in single-step, dsp_mul

---
 rtl/core/mul.sv | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'rtl/core/mul.sv')

diff --git a/rtl/core/mul.sv b/rtl/core/mul.sv
index a05aff7..7c30d0c 100644
--- a/rtl/core/mul.sv
+++ b/rtl/core/mul.sv
@@ -22,7 +22,7 @@ module core_mul
 	             ready     // 1 cuando la multiplicación está lista
 );
 
-	logic wait_state;
+	logic[1:0] wait_state;
 	dword c, q;
 
 	assign ready = !start && wait_state == {$bits(wait_state){1'b0}};
@@ -34,7 +34,7 @@ module core_mul
 	dsp_mul it
 	(
 		.clock0(clk),
-		.aclr0(rst_n),
+		.aclr0(0), //TODO: parece ser active-high, así que no puede ir a rst_n
 		.ena0(start || !ready),
 		.dataa_0(a),
 		.datab_0(b),
@@ -58,6 +58,6 @@ module core_mul
 		else if(wait_state > {$bits(wait_state){1'b0}})
 			wait_state <= wait_state - 1;
 		else if(start)
-			wait_state <= 1;
+			wait_state <= {$bits(wait_state){1'b1}};
 
 endmodule
-- 
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