From ff71bcd0c5425c168f111b8f4a92d0a90a6c9c31 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Sun, 11 Dec 2022 14:48:08 -0600
Subject: Implement data aborts

---
 rtl/core/mmu/mmu.sv      | 12 +++++++++++-
 rtl/core/mmu/pagewalk.sv | 17 ++++++++++++++---
 2 files changed, 25 insertions(+), 4 deletions(-)

(limited to 'rtl/core/mmu')

diff --git a/rtl/core/mmu/mmu.sv b/rtl/core/mmu/mmu.sv
index 504e447..91986db 100644
--- a/rtl/core/mmu/mmu.sv
+++ b/rtl/core/mmu/mmu.sv
@@ -26,8 +26,12 @@ module core_mmu
 	                  bus_write,
 	                  insn_ready,
 	                  data_ready,
+	                  data_fault,
 	output word       insn_data_rd,
-	                  data_data_rd
+	                  data_data_rd,
+
+	output logic      fault_register,
+	output ptr        fault_addr
 );
 
 	ptr iphys_addr, dphys_addr;
@@ -35,15 +39,19 @@ module core_mmu
 	logic iphys_start, dphys_start, iphys_ready, dphys_ready, dphys_write;
 	logic[3:0] dphys_data_be;
 
+	assign fault_register = data_fault;
+
 	core_mmu_pagewalk iwalk
 	(
 		.core_addr(insn_addr),
 		.core_start(insn_start),
 		.core_write(0),
 		.core_ready(insn_ready),
+		.core_fault(),
 		.core_data_wr(0),
 		.core_data_be(0),
 		.core_data_rd(insn_data_rd),
+		.core_fault_addr(),
 
 		.bus_addr(iphys_addr),
 		.bus_start(iphys_start),
@@ -62,9 +70,11 @@ module core_mmu
 		.core_start(data_start),
 		.core_write(data_write),
 		.core_ready(data_ready),
+		.core_fault(data_fault),
 		.core_data_wr(data_data_wr),
 		.core_data_be(data_data_be),
 		.core_data_rd(data_data_rd),
+		.core_fault_addr(fault_addr),
 
 		.bus_addr(dphys_addr),
 		.bus_start(dphys_start),
diff --git a/rtl/core/mmu/pagewalk.sv b/rtl/core/mmu/pagewalk.sv
index b16ce26..be4aa8b 100644
--- a/rtl/core/mmu/pagewalk.sv
+++ b/rtl/core/mmu/pagewalk.sv
@@ -25,7 +25,9 @@ module core_mmu_pagewalk
 	                  bus_write,
 
 	output logic      core_ready,
-	output word       core_data_rd
+	                  core_fault,
+	output word       core_data_rd,
+	output ptr        core_fault_addr
 );
 
 	enum int unsigned
@@ -71,7 +73,9 @@ module core_mmu_pagewalk
 			bus_data_wr <= 0;
 
 			core_ready <= 0;
+			core_fault <= 0;
 			core_data_rd <= 0;
+			core_fault_addr <= 0;
 		end else begin
 			if(bus_start)
 				bus_start <= 0;
@@ -79,6 +83,9 @@ module core_mmu_pagewalk
 			if(core_ready)
 				core_ready <= 0;
 
+			if(core_fault)
+				core_fault <= 0;
+
 			unique case(state)
 				IDLE:
 					if(core_start) begin
@@ -157,8 +164,12 @@ module core_mmu_pagewalk
 						core_data_rd <= bus_data_rd;
 					end
 
-				//TODO
-				FAULT: ;
+				FAULT: begin
+					state <= IDLE;
+					core_fault <= 1;
+					core_ready <= 1;
+					core_fault_addr <= target;
+				end
 			endcase
 		end
 
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