From 70d7dc9489f4d5b91d8138e0a341eec4ad7f15b0 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Mon, 2 Oct 2023 01:46:44 -0600 Subject: rtl: implement exclusive monitor datapath --- rtl/core/mmu/arbiter.sv | 13 ++++++++++++- rtl/core/mmu/mmu.sv | 24 +++++++++++++++++++++--- rtl/core/mmu/pagewalk.sv | 15 ++++++++++++++- 3 files changed, 47 insertions(+), 5 deletions(-) (limited to 'rtl/core/mmu') diff --git a/rtl/core/mmu/arbiter.sv b/rtl/core/mmu/arbiter.sv index 5a75ddf..b0da7c8 100644 --- a/rtl/core/mmu/arbiter.sv +++ b/rtl/core/mmu/arbiter.sv @@ -4,6 +4,7 @@ module core_mmu_arbiter rst_n, input logic bus_ready, + bus_ex_fail, input word bus_data_rd, data_data_wr, input ptr insn_addr, @@ -11,6 +12,7 @@ module core_mmu_arbiter input logic insn_start, data_start, data_write, + data_ex_lock, input logic[3:0] data_data_be, output word bus_data_wr, @@ -18,8 +20,10 @@ module core_mmu_arbiter output ptr bus_addr, output logic bus_start, bus_write, + bus_ex_lock, insn_ready, data_ready, + data_ex_fail, output word insn_data_rd, data_data_rd ); @@ -32,9 +36,10 @@ module core_mmu_arbiter ptr hold_addr; word hold_data_wr; - logic active, hold_start, hold_write, hold_issue, hold_free, transition; + logic active, hold_ex_lock, hold_start, hold_write, hold_issue, hold_free, transition; logic[3:0] hold_data_be; + assign data_ex_fail = bus_ex_fail; assign insn_data_rd = bus_data_rd; assign data_data_rd = bus_data_rd; @@ -66,6 +71,7 @@ module core_mmu_arbiter bus_write = 0; bus_start = insn_start; bus_data_be = 4'b1111; + bus_ex_lock = 0; end DATA: begin @@ -73,6 +79,7 @@ module core_mmu_arbiter bus_write = data_write; bus_start = data_start; bus_data_be = data_data_be; + bus_ex_lock = data_ex_lock; end endcase @@ -82,6 +89,7 @@ module core_mmu_arbiter bus_start = 1; bus_data_wr = hold_data_wr; bus_data_be = hold_data_be; + bus_ex_lock = hold_ex_lock; end end @@ -95,6 +103,7 @@ module core_mmu_arbiter hold_write <= 0; hold_data_wr <= 0; hold_data_be <= 0; + hold_ex_lock <= 0; end else begin master <= next_master; active <= bus_start || (active && !bus_ready); @@ -107,6 +116,7 @@ module core_mmu_arbiter hold_write <= data_write; hold_data_wr <= data_data_wr; hold_data_be <= data_data_be; + hold_ex_lock <= data_ex_lock; end DATA: begin @@ -114,6 +124,7 @@ module core_mmu_arbiter hold_start <= insn_start; hold_write <= 0; hold_data_be <= 4'b1111; + hold_ex_lock <= 0; end endcase end diff --git a/rtl/core/mmu/mmu.sv b/rtl/core/mmu/mmu.sv index b6c3668..22dfc3b 100644 --- a/rtl/core/mmu/mmu.sv +++ b/rtl/core/mmu/mmu.sv @@ -12,6 +12,7 @@ module core_mmu input word mmu_dac, input logic bus_ready, + bus_ex_fail, input word bus_data_rd, data_data_wr, input ptr insn_addr, @@ -19,6 +20,7 @@ module core_mmu input logic insn_start, data_start, data_write, + data_ex_lock, data_user, input logic[3:0] data_data_be, @@ -27,10 +29,12 @@ module core_mmu output ptr bus_addr, output logic bus_start, bus_write, + bus_ex_lock, insn_ready, insn_fault, data_ready, data_fault, + data_ex_fail, output word insn_data_rd, data_data_rd, @@ -43,9 +47,11 @@ module core_mmu ptr iphys_addr, dphys_addr; word iphys_data_rd, dphys_data_rd, dphys_data_wr; - logic iphys_start, dphys_start, iphys_ready, dphys_ready, dphys_write; logic[3:0] dphys_data_be; + logic iphys_start, dphys_start, iphys_ready, dphys_ready, dphys_write, + dphys_ex_fail, dphys_ex_lock; + assign fault_register = data_fault; core_mmu_pagewalk iwalk @@ -54,10 +60,13 @@ module core_mmu .core_start(insn_start), .core_write(0), .core_ready(insn_ready), - .core_fault(insn_fault), .core_data_wr(0), .core_data_be(0), .core_data_rd(insn_data_rd), + .core_ex_fail(), + .core_ex_lock(0), + + .core_fault(insn_fault), .core_fault_addr(), .core_fault_page(), .core_fault_type(), @@ -70,6 +79,8 @@ module core_mmu .bus_data_wr(), .bus_data_be(), .bus_data_rd(iphys_data_rd), + .bus_ex_fail(0), + .bus_ex_lock(), .* ); @@ -80,10 +91,13 @@ module core_mmu .core_start(data_start), .core_write(data_write), .core_ready(data_ready), - .core_fault(data_fault), .core_data_wr(data_data_wr), .core_data_be(data_data_be), .core_data_rd(data_data_rd), + .core_ex_fail(data_ex_fail), + .core_ex_lock(data_ex_lock), + + .core_fault(data_fault), .core_fault_addr(fault_addr), .core_fault_page(fault_page), .core_fault_type(fault_type), @@ -96,6 +110,8 @@ module core_mmu .bus_data_wr(dphys_data_wr), .bus_data_be(dphys_data_be), .bus_data_rd(dphys_data_rd), + .bus_ex_fail(dphys_ex_fail), + .bus_ex_lock(dphys_ex_lock), .privileged(privileged && !data_user), .* @@ -115,6 +131,8 @@ module core_mmu .data_data_wr(dphys_data_wr), .data_data_be(dphys_data_be), .data_data_rd(dphys_data_rd), + .data_ex_fail(dphys_ex_fail), + .data_ex_lock(dphys_ex_lock), .* ); diff --git a/rtl/core/mmu/pagewalk.sv b/rtl/core/mmu/pagewalk.sv index 13da8c9..70c932c 100644 --- a/rtl/core/mmu/pagewalk.sv +++ b/rtl/core/mmu/pagewalk.sv @@ -12,6 +12,7 @@ module core_mmu_pagewalk input word mmu_dac, input logic bus_ready, + bus_ex_fail, input word bus_data_rd, input ptr core_addr, @@ -19,15 +20,18 @@ module core_mmu_pagewalk input logic[3:0] core_data_be, input logic core_start, core_write, + core_ex_lock, output ptr bus_addr, output word bus_data_wr, output logic[3:0] bus_data_be, output logic bus_start, bus_write, + bus_ex_lock, output word core_data_rd, output logic core_ready, + core_ex_fail, core_fault, core_fault_page, output ptr core_fault_addr, @@ -81,7 +85,7 @@ module core_mmu_pagewalk ptr target; word hold_data; - logic hold_write; + logic hold_write, hold_ex_lock; logic[3:0] hold_be; always_comb begin @@ -138,15 +142,18 @@ module core_mmu_pagewalk hold_be <= 0; hold_data <= 0; hold_write <= 0; + hold_ex_lock <= 0; bus_addr <= 0; bus_start <= 0; bus_write <= 0; + bus_ex_lock <= 0; bus_data_be <= 0; bus_data_wr <= 0; core_ready <= 0; core_fault <= 0; + core_ex_fail <= 0; core_data_rd <= 0; core_fault_page <= 0; core_fault_addr <= 0; @@ -171,14 +178,17 @@ module core_mmu_pagewalk hold_be <= core_data_be; hold_data <= core_data_wr; hold_write <= core_write; + hold_ex_lock <= core_ex_lock; state <= L1; bus_addr <= {mmu_ttbr, core_addr `MMU_L1_INDEX}; bus_write <= 0; + bus_ex_lock <= 0; end else begin state <= DATA; bus_addr <= core_addr; bus_write <= core_write; + bus_ex_lock <= core_ex_lock; bus_data_wr <= core_data_wr; bus_data_be <= core_data_be; end @@ -198,6 +208,7 @@ module core_mmu_pagewalk state <= DATA; bus_addr <= {section.base, target `MMU_SECTION_INDEX}; bus_write <= hold_write; + bus_ex_lock <= hold_ex_lock; bus_data_wr <= hold_data; bus_data_be <= hold_be; end @@ -211,6 +222,7 @@ module core_mmu_pagewalk state <= DATA; bus_write <= hold_write; + bus_ex_lock <= hold_ex_lock; bus_data_wr <= hold_data; bus_data_be <= hold_be; @@ -229,6 +241,7 @@ module core_mmu_pagewalk if(bus_ready) begin state <= IDLE; core_ready <= 1; + core_ex_fail <= bus_ex_fail; core_data_rd <= bus_data_rd; end -- cgit v1.2.3