From 5d798386c3b1c1dc45a2fbc382c9367ccc27c524 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Wed, 9 Nov 2022 09:25:48 -0600
Subject: Implement reset

---
 rtl/core/mmu/mmu.sv | 60 ++++++++++++++++++++++++++---------------------------
 1 file changed, 30 insertions(+), 30 deletions(-)

(limited to 'rtl/core/mmu')

diff --git a/rtl/core/mmu/mmu.sv b/rtl/core/mmu/mmu.sv
index bf37cb0..185fb6b 100644
--- a/rtl/core/mmu/mmu.sv
+++ b/rtl/core/mmu/mmu.sv
@@ -1,6 +1,7 @@
 module core_mmu
 (
 	input  logic clk,
+	             rst_n,
 
 	input  logic bus_ready,
 	input  word  bus_data_rd,
@@ -80,35 +81,34 @@ module core_mmu
 		end
 	end
 
-	always_ff @(posedge clk) begin
-		master <= next_master;
-		active <= bus_start || (active && !bus_ready);
-
-		if(hold_free)
-			unique case(next_master)
-				INSN: begin
-					hold_start <= data_start;
-					hold_addr <= data_addr;
-					hold_write <= data_write;
-					hold_data_wr <= data_data_wr;
-				end
-
-				DATA: begin
-					hold_start <= insn_start;
-					hold_addr <= insn_addr;
-					hold_write <= 0;
-				end
-			endcase
-	end
-
-	initial begin
-		master = INSN;
-		active = 0;
-
-		hold_addr = 30'b0;
-		hold_start = 0;
-		hold_write = 0;
-		hold_data_wr = 0;
-	end
+	always_ff @(posedge clk or negedge rst_n)
+		if(!rst_n) begin
+			master <= INSN;
+			active <= 0;
+
+			hold_addr <= 30'b0;
+			hold_start <= 0;
+			hold_write <= 0;
+			hold_data_wr <= 0;
+		end else begin
+			master <= next_master;
+			active <= bus_start || (active && !bus_ready);
+
+			if(hold_free)
+				unique case(next_master)
+					INSN: begin
+						hold_start <= data_start;
+						hold_addr <= data_addr;
+						hold_write <= data_write;
+						hold_data_wr <= data_data_wr;
+					end
+
+					DATA: begin
+						hold_start <= insn_start;
+						hold_addr <= insn_addr;
+						hold_write <= 0;
+					end
+				endcase
+		end
 
 endmodule
-- 
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