From 46eae9622ab6f1a39c6253dc0998e03c57513510 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Sun, 18 Dec 2022 13:19:55 -0600 Subject: Implement mode-translated memory accesses --- rtl/core/mmu/mmu.sv | 2 ++ 1 file changed, 2 insertions(+) (limited to 'rtl/core/mmu') diff --git a/rtl/core/mmu/mmu.sv b/rtl/core/mmu/mmu.sv index f8e808b..b6c3668 100644 --- a/rtl/core/mmu/mmu.sv +++ b/rtl/core/mmu/mmu.sv @@ -19,6 +19,7 @@ module core_mmu input logic insn_start, data_start, data_write, + data_user, input logic[3:0] data_data_be, output word bus_data_wr, @@ -96,6 +97,7 @@ module core_mmu .bus_data_be(dphys_data_be), .bus_data_rd(dphys_data_rd), + .privileged(privileged && !data_user), .* ); -- cgit v1.2.3