From d9dfa098323bc9ffdc9e976bd4106efc75b2954a Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Tue, 15 Nov 2022 23:18:09 -0600
Subject: Implemente byte-enable signal in stores

---
 rtl/core/mmu/mmu.sv | 38 ++++++++++++++++++++------------------
 1 file changed, 20 insertions(+), 18 deletions(-)

(limited to 'rtl/core/mmu/mmu.sv')

diff --git a/rtl/core/mmu/mmu.sv b/rtl/core/mmu/mmu.sv
index a4be70e..a909537 100644
--- a/rtl/core/mmu/mmu.sv
+++ b/rtl/core/mmu/mmu.sv
@@ -1,25 +1,27 @@
 module core_mmu
 (
-	input  logic clk,
-	             rst_n,
+	input  logic      clk,
+	                  rst_n,
 
-	input  logic bus_ready,
-	input  word  bus_data_rd,
-	             data_data_wr,
-	input  ptr   insn_addr,
-	             data_addr,
-	input  logic insn_start,
-	             data_start,
-	             data_write,
+	input  logic      bus_ready,
+	input  word       bus_data_rd,
+	                  data_data_wr,
+	input  ptr        insn_addr,
+	                  data_addr,
+	input  logic      insn_start,
+	                  data_start,
+	                  data_write,
+	input  logic[3:0] data_data_be,
 
-	output word  bus_data_wr,
-	output ptr   bus_addr,
-	output logic bus_start,
-	             bus_write,
-	             insn_ready,
-	             data_ready,
-	output word  insn_data_rd,
-	             data_data_rd
+	output word       bus_data_wr,
+	output logic[3:0] bus_data_be,
+	output ptr        bus_addr,
+	output logic      bus_start,
+	                  bus_write,
+	                  insn_ready,
+	                  data_ready,
+	output word       insn_data_rd,
+	                  data_data_rd
 );
 
 	//TODO
-- 
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