From b5f43ef8431532b1e0b498a88072fdfd2cf81ac9 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Sun, 25 Sep 2022 17:46:38 -0600
Subject: Implement ALU

---
 rtl/core/isa.sv | 17 -----------------
 1 file changed, 17 deletions(-)

(limited to 'rtl/core/isa.sv')

diff --git a/rtl/core/isa.sv b/rtl/core/isa.sv
index 256c1cc..710b11b 100644
--- a/rtl/core/isa.sv
+++ b/rtl/core/isa.sv
@@ -64,23 +64,6 @@ typedef logic[3:0] reg_num;
 `define FIELD_DATA_RD      [15:12]
 `define FIELD_DATA_SHIFTER [11:0]
 
-`define DATA_AND 4'b0000
-`define DATA_EOR 4'b0001
-`define DATA_SUB 4'b0010
-`define DATA_RSB 4'b0011
-`define DATA_ADD 4'b0100
-`define DATA_ADC 4'b0101
-`define DATA_SBC 4'b0110
-`define DATA_RSC 4'b0111
-`define DATA_TST 4'b1000
-`define DATA_TEQ 4'b1001
-`define DATA_CMP 4'b1010
-`define DATA_CMN 4'b1011
-`define DATA_ORR 4'b1100
-`define DATA_MOV 4'b1101
-`define DATA_BIC 4'b1110
-`define DATA_MVN 4'b1111
-
 // Instrucciones de multiplicación
 
 `define INSN_MUL   28'b0000000_?_????_0000_????_1001_????
-- 
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