From 5dc62fde35731279e5ef4c7b334cb97d4f24f656 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Sun, 25 Sep 2022 15:00:25 -0600
Subject: Implement register file

---
 rtl/core/isa.sv | 1 +
 1 file changed, 1 insertion(+)

(limited to 'rtl/core/isa.sv')

diff --git a/rtl/core/isa.sv b/rtl/core/isa.sv
index be012d1..256c1cc 100644
--- a/rtl/core/isa.sv
+++ b/rtl/core/isa.sv
@@ -6,6 +6,7 @@
 
 typedef logic[3:0] reg_num;
 
+`define R14 4'b1110
 `define R15 4'b1111
 
 `define COND_EQ 4'b0000
-- 
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