From f3b18ead59ae02f95dabbf0a1dea40873a816975 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Sun, 21 Jan 2024 06:23:46 -0600
Subject: rtl: refactor filenames and directory hierarchy

---
 rtl/core/fetch/fetch.sv    | 74 ----------------------------------------
 rtl/core/fetch/prefetch.sv | 84 ----------------------------------------------
 2 files changed, 158 deletions(-)
 delete mode 100644 rtl/core/fetch/fetch.sv
 delete mode 100644 rtl/core/fetch/prefetch.sv

(limited to 'rtl/core/fetch')

diff --git a/rtl/core/fetch/fetch.sv b/rtl/core/fetch/fetch.sv
deleted file mode 100644
index 279d2c2..0000000
--- a/rtl/core/fetch/fetch.sv
+++ /dev/null
@@ -1,74 +0,0 @@
-`include "core/uarch.sv"
-
-module core_fetch
-#(parameter PREFETCH_ORDER=2)
-(
-	input  logic clk,
-	             rst_n,
-	             stall,
-	             fault,
-	             fetched,
-	             explicit_branch /*verilator public*/ /*verilator forceable*/,
-	             wr_pc,
-	             prefetch_flush,
-	input  ptr   branch_target,
-	             porch_insn_pc,
-	input  word  wr_current,
-	             fetch_data,
-
-	output logic fetch,
-	             flush,
-	             nop,
-	output word  insn,
-	output ptr   insn_pc,
-	             addr,
-	             fetch_head,
-	output logic insn_abort
-);
-
-	ptr target /*verilator public*/ /*verilator forceable*/, hold_addr;
-	logic branch, prefetch_ready, fetched_valid, discard, pending, next_pending;
-
-	assign fetch = prefetch_ready && !discard;
-	assign flush = branch || prefetch_flush;
-	assign branch = explicit_branch || wr_pc;
-	assign target = wr_pc ? wr_current[31:2] : branch_target; //TODO: alignment exception
-	assign next_pending = fetch || (pending && !fetched);
-	assign fetched_valid = fetched && !discard;
-
-	core_prefetch #(.ORDER(PREFETCH_ORDER)) prefetch
-	(
-		.head(fetch_head),
-		.fetched(fetched_valid),
-		.fetch(prefetch_ready),
-		.*
-	);
-
-	always_comb begin
-		if(branch)
-			fetch_head = target;
-		else if(prefetch_flush)
-			fetch_head = porch_insn_pc;
-		else
-			fetch_head = {30{1'bx}};
-
-		if(flush)
-			addr = fetch_head;
-		else if(fetch && fetched_valid)
-			addr = hold_addr + 1;
-		else
-			addr = hold_addr;
-	end
-
-	always_ff @(posedge clk or negedge rst_n)
-		if(!rst_n) begin
-			pending <= 0;
-			discard <= 0;
-			hold_addr <= 0;
-		end else begin
-			pending <= next_pending;
-			discard <= next_pending && (discard || flush);
-			hold_addr <= addr;
-		end
-
-endmodule
diff --git a/rtl/core/fetch/prefetch.sv b/rtl/core/fetch/prefetch.sv
deleted file mode 100644
index 719ad95..0000000
--- a/rtl/core/fetch/prefetch.sv
+++ /dev/null
@@ -1,84 +0,0 @@
-`include "core/uarch.sv"
-
-module core_prefetch
-#(parameter ORDER=2)
-(
-	input  logic clk,
-	             rst_n,
-	             stall,
-	             flush,
-	             fault,
-	             fetched,
-	input  word  fetch_data,
-	input  ptr   head,
-
-	output word  insn,
-	output ptr   insn_pc,
-	output logic fetch,
-	             nop,
-	             insn_abort
-);
-
-	localparam SIZE = (1 << ORDER) - 1;
-
-	ptr next_pc;
-	logic faults[SIZE];
-	logic[31:0] prefetch[SIZE];
-	logic[ORDER - 1:0] valid;
-
-	assign nop = flush ? 1 : ~|valid;
-	assign insn = flush ? `NOP : prefetch[0];
-	assign fetch = !stall || ~&valid;
-	assign next_pc = ~stall & |valid ? insn_pc + 1 : insn_pc;
-	assign insn_abort = flush ? 0 : faults[0];
-
-	always_ff @(posedge clk or negedge rst_n)
-		if(!rst_n) begin
-			valid <= 0;
-			insn_pc <= 0;
-
-			faults[SIZE - 1] <= 0;
-			prefetch[SIZE - 1] <= `NOP;
-		end else begin
-			insn_pc <= flush ? head : next_pc;
-
-			if(flush) begin
-				faults[SIZE - 1] <= 0;
-				prefetch[SIZE - 1] <= `NOP;
-			end else if(fetched && valid == SIZE - 1 + {{(ORDER - 1){1'b0}}, !stall}) begin
-				faults[SIZE - 1] <= fault;
-				prefetch[SIZE - 1] <= fetch_data;
-			end else if(!stall) begin
-				faults[SIZE - 1] <= 0;
-				prefetch[SIZE - 1] <= `NOP;
-			end
-
-			if(flush)
-				valid <= 0;
-			else if(fetched & ((stall & ~&valid) | ~|valid))
-				valid <= valid + 1;
-			else if(~stall & ~fetched & |valid)
-				valid <= valid - 1;
-		end
-
-	genvar i;
-	generate
-		for(i = 0; i < SIZE - 1; ++i) begin: prefetch_slots
-			always_ff @(posedge clk or negedge rst_n)
-				if(!rst_n) begin
-					faults[i] <= 0;
-					prefetch[i] <= `NOP;
-				end else if(flush) begin
-					faults[i] <= 0;
-					prefetch[i] <= `NOP;
-			end else if(fetched & (~(|i | |valid) | (valid == i + {{(ORDER - 1){1'b0}}, ~stall}))) begin
-					faults[i] <= fault;
-					prefetch[i] <= fetch_data;
-				end else if(~stall) begin
-					faults[i] <= faults[i + 1];
-					prefetch[i] <= prefetch[i + 1];
-				end
-		end
-	endgenerate
-
-endmodule
-- 
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