From ec152d814af82524cf68df95d7f06b9b70c0d0d0 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Sat, 15 Oct 2022 19:31:55 -0600 Subject: Rework bus architecture --- rtl/core/fetch/prefetch.sv | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) (limited to 'rtl/core/fetch/prefetch.sv') diff --git a/rtl/core/fetch/prefetch.sv b/rtl/core/fetch/prefetch.sv index 486ec96..4025339 100644 --- a/rtl/core/fetch/prefetch.sv +++ b/rtl/core/fetch/prefetch.sv @@ -23,19 +23,16 @@ module core_prefetch assign insn = flush ? `NOP : prefetch[0]; assign next_pc = ~stall & |valid ? insn_pc + 1 : insn_pc; - - always_comb - if((valid == SIZE - 2) & fetched) - fetch = 0; - else - fetch = ~&valid; + assign fetch = !stall || ~&valid; always_ff @(posedge clk) begin insn_pc <= flush ? head : next_pc; - if(~flush & fetched & (valid == SIZE - 1)) + if(flush) + prefetch[SIZE - 1] <= `NOP; + else if(fetched && valid == SIZE - 1 + {{(ORDER - 1){1'b0}}, !stall}) prefetch[SIZE - 1] <= fetch_data; - else + else if(!stall) prefetch[SIZE - 1] <= `NOP; if(flush) -- cgit v1.2.3