From ec152d814af82524cf68df95d7f06b9b70c0d0d0 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Sat, 15 Oct 2022 19:31:55 -0600 Subject: Rework bus architecture --- rtl/core/fetch/fetch.sv | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) (limited to 'rtl/core/fetch/fetch.sv') diff --git a/rtl/core/fetch/fetch.sv b/rtl/core/fetch/fetch.sv index a57c679..e8c6a9b 100644 --- a/rtl/core/fetch/fetch.sv +++ b/rtl/core/fetch/fetch.sv @@ -17,7 +17,7 @@ module core_fetch addr ); - ptr next_pc, head; + ptr next_pc, head, hold_addr; logic fetched_valid, do_flush, discard; assign do_flush = branch | flush; @@ -30,7 +30,7 @@ module core_fetch .* ); - always_comb + always_comb begin if(branch) head = target; else if(flush) @@ -38,17 +38,21 @@ module core_fetch else head = {30{1'bx}}; - always_ff @(posedge clk) begin if(do_flush) - addr <= head; + addr = head; else if(fetched_valid) - addr <= addr + 1; + addr = hold_addr + 1; + else + addr = hold_addr; + end + always_ff @(posedge clk) begin discard <= discard ? ~fetched : do_flush & fetch; + hold_addr <= addr; end initial begin - addr = 0; + hold_addr = 0; discard = 0; end -- cgit v1.2.3