From 0284628a47d5b4797c89f6846b9efee3f1243b94 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Sun, 11 Dec 2022 23:00:37 -0600 Subject: Implement register writes from gdb --- rtl/core/fetch/fetch.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'rtl/core/fetch/fetch.sv') diff --git a/rtl/core/fetch/fetch.sv b/rtl/core/fetch/fetch.sv index c024e7d..ba9d677 100644 --- a/rtl/core/fetch/fetch.sv +++ b/rtl/core/fetch/fetch.sv @@ -7,7 +7,7 @@ module core_fetch rst_n, stall, fetched, - explicit_branch, + explicit_branch /*verilator public*/ /*verilator forceable*/, wr_pc, prefetch_flush, input ptr branch_target, @@ -24,7 +24,7 @@ module core_fetch fetch_head ); - ptr hold_addr, target; + ptr target /*verilator public*/ /*verilator forceable*/, hold_addr; logic branch, prefetch_ready, fetched_valid, discard, pending, next_pending; assign fetch = prefetch_ready && !discard; -- cgit v1.2.3