From b5a065227bd176b85765461ac2a791fb0cff1c72 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Mon, 31 Oct 2022 15:25:38 -0600 Subject: Implement multiplication decode --- rtl/core/decode/mul.sv | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 rtl/core/decode/mul.sv (limited to 'rtl/core/decode/mul.sv') diff --git a/rtl/core/decode/mul.sv b/rtl/core/decode/mul.sv new file mode 100644 index 0000000..f67435c --- /dev/null +++ b/rtl/core/decode/mul.sv @@ -0,0 +1,34 @@ +`include "core/decode/isa.sv" +`include "core/uarch.sv" + +module core_decode_mul +( + input word insn, + + output mul_decode decode, + output reg_num rd, + rs, + rm, + output logic update_flags +); + + logic long_mul; + reg_num short_rd, rn; + + assign rd = long_mul ? rn : short_rd; + assign rs = insn `FIELD_MUL_RS; + assign rm = insn `FIELD_MUL_RM; + assign update_flags = insn `FIELD_MUL_S; + + assign decode.enable = 0; + assign decode.add = insn `FIELD_MUL_ACC; + assign decode.long_mul = long_mul; + assign decode.signed_mul = insn `FIELD_MUL_SIGNED; + assign decode.r_add_lo = long_mul ? rn : short_rd; + assign decode.r_add_hi = short_rd; + + assign long_mul = insn `FIELD_MUL_LONG; + assign short_rd = insn `FIELD_MUL_RD; + assign rn = insn `FIELD_MUL_RN; + +endmodule -- cgit v1.2.3