From 683352ce030923bdef3cf4fe90d6cb73f4f74529 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Wed, 16 Nov 2022 16:46:52 -0600
Subject: Implement psr read/write logic

---
 rtl/core/decode/isa.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'rtl/core/decode/isa.sv')

diff --git a/rtl/core/decode/isa.sv b/rtl/core/decode/isa.sv
index 4f2578d..1273a8b 100644
--- a/rtl/core/decode/isa.sv
+++ b/rtl/core/decode/isa.sv
@@ -194,7 +194,7 @@
 
 `define GROUP_MSR 28'b0_0_?_1_0_?_1_0_????_1111_0000_0000_????
 
-`define FIELD_MRS_R    [24]
+`define FIELD_MRS_R    [22]
 `define FIELD_MRS_RD   [15:12]
 `define FIELD_MSR_I    [25]
 `define FIELD_MSR_R    [22]
-- 
cgit v1.2.3