From ed0bd705f94f6aea568ec8405534984a37770f21 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Mon, 25 Sep 2023 19:12:49 -0600
Subject: rtl/core, tb: replace bus_master with a new top-level module

---
 rtl/core/decode/data_dec.sv | 65 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 65 insertions(+)
 create mode 100644 rtl/core/decode/data_dec.sv

(limited to 'rtl/core/decode/data_dec.sv')

diff --git a/rtl/core/decode/data_dec.sv b/rtl/core/decode/data_dec.sv
new file mode 100644
index 0000000..f744972
--- /dev/null
+++ b/rtl/core/decode/data_dec.sv
@@ -0,0 +1,65 @@
+`include "core/decode/isa.sv"
+`include "core/uarch.sv"
+
+module core_decode_data
+(
+	input  word        insn,
+
+	output data_decode decode,
+	output logic       snd_is_imm,
+	                   snd_shift_by_reg_if_reg,
+	                   writeback,
+	                   conditional,
+	                   update_flags,
+	                   restore_spsr
+);
+
+	alu_op op;
+	reg_num rn, rd;
+	logic uses_rn;
+
+	assign decode.op = op;
+	assign decode.rn = rn;
+	assign decode.rd = rd;
+	assign decode.uses_rn = uses_rn;
+
+	assign rn = insn `FIELD_DATA_RN;
+	assign rd = insn `FIELD_DATA_RD;
+	assign op = insn `FIELD_DATA_OPCODE;
+
+	assign snd_is_imm = insn `FIELD_DATA_IMM;
+	assign snd_shift_by_reg_if_reg = insn `FIELD_DATA_REGSHIFT;
+
+	always_comb begin
+		unique case(op)
+			`ALU_ADC, `ALU_SBC, `ALU_RSC:
+				conditional = 1;
+
+			default:
+				conditional = 0;
+		endcase
+
+		unique case(op)
+			`ALU_CMP, `ALU_CMN, `ALU_TST, `ALU_TEQ:
+				writeback = 0;
+
+			default:
+				writeback = 1;
+		endcase
+
+		unique case(op)
+			`ALU_MOV, `ALU_MVN:
+				uses_rn = 0;
+
+			default:
+				uses_rn = 1;
+		endcase
+
+		update_flags = insn `FIELD_DATA_S;
+		restore_spsr = (rd == `R15) & update_flags;
+
+		if(restore_spsr)
+			update_flags = 0;
+	end
+
+endmodule
-- 
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