From fa370016708149976c748c14eadad1f89cf5a8ea Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Sun, 25 Sep 2022 19:55:29 -0600 Subject: Refactor CPSR and uarch.sv --- rtl/core/cycles.sv | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) (limited to 'rtl/core/cycles.sv') diff --git a/rtl/core/cycles.sv b/rtl/core/cycles.sv index c5ad62f..0f6ce15 100644 --- a/rtl/core/cycles.sv +++ b/rtl/core/cycles.sv @@ -1,4 +1,3 @@ -`include "core/psr.sv" `include "core/uarch.sv" module core_cycles @@ -11,7 +10,6 @@ module core_cycles input ptr decode_branch_offset, input alu_op decode_data_op, input ptr fetch_insn_pc, - input psr_flags alu_flags, output logic stall, branch, @@ -21,9 +19,7 @@ module core_cycles pc, pc_visible, output psr_mode reg_mode, - output alu_op data_op, - output psr_flags flags, - next_flags + output alu_op data_op ); enum @@ -34,12 +30,10 @@ module core_cycles assign stall = next_cycle != EXECUTE; assign pc_visible = pc + 2; assign next_cycle = EXECUTE; //TODO - assign next_flags = alu_flags; //TODO assign reg_mode = `MODE_SVC; //TODO always_ff @(posedge clk) begin cycle <= next_cycle; - flags <= next_flags; if(next_cycle == EXECUTE) begin branch <= 0; -- cgit v1.2.3