From f65e5611fde5e1c3e3a509cb2f3ffcafce5bbd33 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Sun, 25 Sep 2022 17:47:38 -0600
Subject: Implement PSR flag handling

---
 rtl/core/cycles.sv | 41 ++++++++++++++++++++++++++---------------
 1 file changed, 26 insertions(+), 15 deletions(-)

(limited to 'rtl/core/cycles.sv')

diff --git a/rtl/core/cycles.sv b/rtl/core/cycles.sv
index 64d77e6..d52c0b0 100644
--- a/rtl/core/cycles.sv
+++ b/rtl/core/cycles.sv
@@ -1,22 +1,29 @@
+`include "core/psr.sv"
 `include "core/uarch.sv"
 
 module core_cycles
 (
-	input  logic    clk,
-	                decode_execute,
-	                decode_writeback,
-	                decode_branch,
-	input  ptr      decode_branch_offset,
-	input  reg_num  decode_rd,
-	input  ptr      fetch_insn_pc,
-
-	output logic    stall,
-	                branch,
-	                writeback,
-	output ptr      branch_target,
-	                pc,
-	                pc_visible,
-	output psr_mode reg_mode
+	input  logic     clk,
+	                 decode_execute,
+	                 decode_writeback,
+	                 decode_branch,
+	input  reg_num   decode_rd,
+	input  ptr       decode_branch_offset,
+	input  alu_op    decode_data_op,
+	input  ptr       fetch_insn_pc,
+	input  psr_flags alu_flags,
+
+	output logic     stall,
+	                 branch,
+	                 writeback,
+	output reg_num   rd,
+	output ptr       branch_target,
+	                 pc,
+	                 pc_visible,
+	output psr_mode  reg_mode,
+	output alu_op    data_op,
+	output psr_flags flags,
+	                 next_flags
 );
 
 	enum
@@ -27,11 +34,13 @@ module core_cycles
 	assign stall = next_cycle != EXECUTE;
 	assign pc_visible = pc + 2;
 	assign next_cycle = EXECUTE; //TODO
+	assign next_flags = alu_flags; //TODO
 	assign reg_mode = `MODE_SVC; //TODO
 
 	always_ff @(posedge clk) begin
 		cycle <= next_cycle;
 		stall <= next_cycle != EXECUTE;
+		flags <= next_flags;
 
 		if(next_cycle == EXECUTE) begin
 			branch <= 0;
@@ -45,6 +54,8 @@ module core_cycles
 			end
 
 			pc <= fetch_insn_pc;
+			rd <= decode_rd;
+			data_op <= decode_data_op;
 		end
 	end
 
-- 
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