From 43829e0400f0a7aaccbb1ebefb44a38c41749e77 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Sun, 25 Sep 2022 23:21:32 -0600
Subject: Implement shifter decoding

---
 rtl/core/cycles.sv | 41 ++++++++++++++++++++---------------------
 1 file changed, 20 insertions(+), 21 deletions(-)

(limited to 'rtl/core/cycles.sv')

diff --git a/rtl/core/cycles.sv b/rtl/core/cycles.sv
index 3520467..ff4eb34 100644
--- a/rtl/core/cycles.sv
+++ b/rtl/core/cycles.sv
@@ -2,26 +2,25 @@
 
 module core_cycles
 (
-	input  logic     clk,
-	                 dec_execute,
-	                 dec_branch,
-	                 dec_writeback,
-	                 dec_update_flags,
-	input  reg_num   dec_rd,
-	input  ptr       dec_branch_offset,
-	input  alu_op    dec_data_op,
-	input  ptr       fetch_insn_pc,
+	input  logic      clk,
+	                  dec_execute,
+	                  dec_branch,
+	                  dec_writeback,
+	                  dec_update_flags,
+	input  ptr        dec_branch_offset,
+	input  alu_decode dec_alu,
+	input  ptr        fetch_insn_pc,
 
-	output logic     stall,
-	                 branch,
-	                 writeback,
-	                 update_flags,
-	output reg_num   rd,
-	output ptr       branch_target,
-	                 pc,
-	                 pc_visible,
-	output psr_mode  reg_mode,
-	output alu_op    data_op
+	output logic      stall,
+	                  branch,
+	                  writeback,
+	                  update_flags,
+	output reg_num    rd,
+	output ptr        branch_target,
+	                  pc,
+	                  pc_visible,
+	output psr_mode   reg_mode,
+	output alu_op     data_op
 );
 
 	enum
@@ -50,8 +49,8 @@ module core_cycles
 			end
 
 			pc <= fetch_insn_pc;
-			rd <= dec_rd;
-			data_op <= dec_data_op;
+			rd <= dec_alu.rd;
+			data_op <= dec_alu.op;
 			update_flags <= dec_update_flags;
 		end
 	end
-- 
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