From f3b18ead59ae02f95dabbf0a1dea40873a816975 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Sun, 21 Jan 2024 06:23:46 -0600
Subject: rtl: refactor filenames and directory hierarchy

---
 rtl/core/cp15/ttbr.sv | 45 ---------------------------------------------
 1 file changed, 45 deletions(-)
 delete mode 100644 rtl/core/cp15/ttbr.sv

(limited to 'rtl/core/cp15/ttbr.sv')

diff --git a/rtl/core/cp15/ttbr.sv b/rtl/core/cp15/ttbr.sv
deleted file mode 100644
index b462955..0000000
--- a/rtl/core/cp15/ttbr.sv
+++ /dev/null
@@ -1,45 +0,0 @@
-`include "core/cp15/map.sv"
-`include "core/mmu/format.sv"
-`include "core/uarch.sv"
-
-module core_cp15_ttbr
-(
-	input  logic     clk,
-	                 rst_n,
-
-	input  logic     load,
-	                 transfer,
-	input  word      write,
-
-	output word      read /*verilator public*/,
-	output mmu_base  mmu_ttbr
-);
-
-	logic s, c;
-	cp15_ttbr read_ttbr, write_ttbr;
-	logic[1:0] rgn;
-
-	assign read = read_ttbr;
-	assign write_ttbr = write;
-
-	assign read_ttbr.s = s;
-	assign read_ttbr.c = c;
-	assign read_ttbr.sbz = 9'd0;
-	assign read_ttbr.rgn = rgn;
-	assign read_ttbr.imp = 0;
-	assign read_ttbr.base = mmu_ttbr;
-
-	always @(posedge clk or negedge rst_n)
-		if(!rst_n) begin
-			s <= 0;
-			c <= 0;
-			rgn <= 0;
-			mmu_ttbr <= 0;
-		end else if(transfer && !load) begin
-			s <= write_ttbr.s;
-			c <= write_ttbr.c;
-			rgn <= write_ttbr.rgn;
-			mmu_ttbr <= write_ttbr.base;
-		end
-
-endmodule
-- 
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