From 6b163a88179ac3073d22622be4991f332529c8bd Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Sat, 10 Dec 2022 19:56:19 -0600 Subject: Expose cp15 signals to core toplevel --- rtl/core/cp15/ttbr.sv | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'rtl/core/cp15/ttbr.sv') diff --git a/rtl/core/cp15/ttbr.sv b/rtl/core/cp15/ttbr.sv index 622dd3f..5162edb 100644 --- a/rtl/core/cp15/ttbr.sv +++ b/rtl/core/cp15/ttbr.sv @@ -11,11 +11,11 @@ module core_cp15_ttbr transfer, input word write, - output word read + output word read, + output mmu_base mmu_ttbr ); logic s, c; - mmu_base base; cp15_ttbr read_ttbr, write_ttbr; logic[1:0] rgn; @@ -27,19 +27,19 @@ module core_cp15_ttbr assign read_ttbr.sbz = 9'd0; assign read_ttbr.rgn = rgn; assign read_ttbr.imp = 0; - assign read_ttbr.base = base; + assign read_ttbr.base = mmu_ttbr; always @(posedge clk or negedge rst_n) if(!rst_n) begin s <= 0; c <= 0; rgn <= 0; - base <= 0; + mmu_ttbr <= 0; end else if(transfer && !load) begin s <= write_ttbr.s; c <= write_ttbr.c; rgn <= write_ttbr.rgn; - base <= write_ttbr.base; + mmu_ttbr <= write_ttbr.base; end endmodule -- cgit v1.2.3