From d006be2e89aa493237f212811ee880ed8b54241b Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Sun, 11 Dec 2022 17:28:03 -0600 Subject: Implement MMU access checks --- rtl/core/cp15/fsr.sv | 43 +++++++++++++++++++++++++++++++++---------- 1 file changed, 33 insertions(+), 10 deletions(-) (limited to 'rtl/core/cp15/fsr.sv') diff --git a/rtl/core/cp15/fsr.sv b/rtl/core/cp15/fsr.sv index 0a7d0d4..c42d16a 100644 --- a/rtl/core/cp15/fsr.sv +++ b/rtl/core/cp15/fsr.sv @@ -1,20 +1,43 @@ -`include "core/uarch.sv" `include "core/cp15/map.sv" +`include "core/mmu/format.sv" +`include "core/uarch.sv" module core_cp15_fsr ( - input logic clk, - rst_n, + input logic clk, + rst_n, + + input logic load, + transfer, + input word write, - input logic load, - transfer, - input cp_opcode op2, - input word write, + input logic fault_register, + fault_page, + input mmu_fault_type fault_type, + input mmu_domain fault_domain, - output word read + output word read ); - //TODO - assign read = 0; + logic fsr_page; + mmu_domain fsr_domain; + mmu_fault_type fsr_type; + + assign read = {24'd0, fsr_domain, fsr_type, fsr_page, 1'b1}; + + always @(posedge clk or negedge rst_n) + if(!rst_n) begin + fsr_page <= 0; + fsr_type <= 0; + fsr_domain <= 0; + end else if(fault_register) begin + fsr_page <= fault_page; + fsr_type <= fault_type; + fsr_domain <= fault_domain; + end else if(transfer && !load) begin + fsr_page <= write[1]; + fsr_type <= write[3:2]; + fsr_domain <= write[7:4]; + end endmodule -- cgit v1.2.3