From ed42ddad4a09ef6919ac3c1ee54ad17f4e8b13bc Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Tue, 1 Nov 2022 23:00:52 -0600 Subject: Add CPUID register --- rtl/core/cp15/cp15.sv | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'rtl/core/cp15/cp15.sv') diff --git a/rtl/core/cp15/cp15.sv b/rtl/core/cp15/cp15.sv index b31ccb7..3855e13 100644 --- a/rtl/core/cp15/cp15.sv +++ b/rtl/core/cp15/cp15.sv @@ -1,4 +1,5 @@ `include "core/uarch.sv" +`include "core/cp15/map.sv" module core_cp15 ( @@ -10,4 +11,30 @@ module core_cp15 output word read ); + logic load; + reg_num crm; + cp_opcode op1, op2; + + assign load = dec.load; + assign crm = dec.crm; + assign op1 = dec.op1; + assign op2 = dec.op2; + + word read_cpuid; + + core_cp15_cpuid cpuid + ( + .read(read_cpuid), + .* + ); + + always_comb + unique case(dec.crn) + `CP15_CRN_CPUID: + read = read_cpuid; + + default: + read = {$bits(read){1'bx}}; + endcase + endmodule -- cgit v1.2.3