From f3b18ead59ae02f95dabbf0a1dea40873a816975 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Sun, 21 Jan 2024 06:23:46 -0600 Subject: rtl: refactor filenames and directory hierarchy --- rtl/core/core_cp15_ttbr.sv | 45 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 rtl/core/core_cp15_ttbr.sv (limited to 'rtl/core/core_cp15_ttbr.sv') diff --git a/rtl/core/core_cp15_ttbr.sv b/rtl/core/core_cp15_ttbr.sv new file mode 100644 index 0000000..3b1a76a --- /dev/null +++ b/rtl/core/core_cp15_ttbr.sv @@ -0,0 +1,45 @@ +`include "core/cp15_map.sv" +`include "core/mmu_format.sv" +`include "core/uarch.sv" + +module core_cp15_ttbr +( + input logic clk, + rst_n, + + input logic load, + transfer, + input word write, + + output word read /*verilator public*/, + output mmu_base mmu_ttbr +); + + logic s, c; + cp15_ttbr read_ttbr, write_ttbr; + logic[1:0] rgn; + + assign read = read_ttbr; + assign write_ttbr = write; + + assign read_ttbr.s = s; + assign read_ttbr.c = c; + assign read_ttbr.sbz = 9'd0; + assign read_ttbr.rgn = rgn; + assign read_ttbr.imp = 0; + assign read_ttbr.base = mmu_ttbr; + + always @(posedge clk or negedge rst_n) + if(!rst_n) begin + s <= 0; + c <= 0; + rgn <= 0; + mmu_ttbr <= 0; + end else if(transfer && !load) begin + s <= write_ttbr.s; + c <= write_ttbr.c; + rgn <= write_ttbr.rgn; + mmu_ttbr <= write_ttbr.base; + end + +endmodule -- cgit v1.2.3