From 87a42e555bf952047e287f4c7810cd538595d5af Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Wed, 15 Nov 2023 19:10:34 -0600 Subject: rtl/smp: implement SMP dead/alive handling --- rtl/core/core.sv | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'rtl/core/core.sv') diff --git a/rtl/core/core.sv b/rtl/core/core.sv index ce51a71..cf63b2d 100644 --- a/rtl/core/core.sv +++ b/rtl/core/core.sv @@ -9,6 +9,7 @@ module core input wire step, input wire cpu_halt, + output wire cpu_alive, output wire cpu_halted, output wire breakpoint, @@ -27,6 +28,8 @@ module core generate if (ID < `CONFIG_CPUS) begin: enable + assign cpu_alive = 1; + ptr addr; word data_wr; logic start, write; @@ -57,6 +60,7 @@ module core .* ); end else begin + assign cpu_alive = 0; assign cpu_halted = 1; assign breakpoint = 0; -- cgit v1.2.3