From ed0bd705f94f6aea568ec8405534984a37770f21 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Mon, 25 Sep 2023 19:12:49 -0600 Subject: rtl/core, tb: replace bus_master with a new top-level module --- rtl/core/control/mul.sv | 67 -------------------------------------- rtl/core/control/mul_fu.sv | 67 ++++++++++++++++++++++++++++++++++++++ rtl/core/control/psr.sv | 81 ---------------------------------------------- rtl/core/control/status.sv | 81 ++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 148 insertions(+), 148 deletions(-) delete mode 100644 rtl/core/control/mul.sv create mode 100644 rtl/core/control/mul_fu.sv delete mode 100644 rtl/core/control/psr.sv create mode 100644 rtl/core/control/status.sv (limited to 'rtl/core/control') diff --git a/rtl/core/control/mul.sv b/rtl/core/control/mul.sv deleted file mode 100644 index 8352435..0000000 --- a/rtl/core/control/mul.sv +++ /dev/null @@ -1,67 +0,0 @@ -`include "core/uarch.sv" - -module core_control_mul -( - input logic clk, - rst_n, - - input insn_decode dec, - input logic mul_ready, - input word rd_value_a, - rd_value_b, - - input ctrl_cycle cycle, - next_cycle, - input logic issue, - - output word mul_a, - mul_b, - mul_c_hi, - mul_c_lo, - output reg_num mul_r_add_hi, - mul_r_add_lo, - output logic mul, - mul_add, - mul_long, - mul_start, - mul_signed -); - - word hold_a, hold_b; - - assign {mul_c_hi, mul_c_lo} = {rd_value_a, rd_value_b}; - assign {mul_a, mul_b} = mul_add ? {hold_a, hold_b} : {rd_value_a, rd_value_b}; - - always_ff @(posedge clk or negedge rst_n) - if(!rst_n) begin - mul <= 0; - mul_add <= 0; - mul_long <= 0; - mul_start <= 0; - mul_signed <= 0; - mul_r_add_hi <= {$bits(mul_r_add_hi){1'b0}}; - mul_r_add_lo <= {$bits(mul_r_add_lo){1'b0}}; - - hold_a <= 0; - hold_b <= 0; - end else begin - mul_start <= 0; - - if(next_cycle.issue) begin - mul <= issue && dec.ctrl.mul; - mul_add <= dec.mul.add; - mul_long <= dec.mul.long_mul; - mul_signed <= dec.mul.signed_mul; - mul_r_add_hi <= dec.mul.r_add_hi; - mul_r_add_lo <= dec.mul.r_add_lo; - end else if(next_cycle.mul) - mul_start <= !cycle.mul; - else if(next_cycle.mul_acc_ld) begin - hold_a <= rd_value_a; - hold_b <= rd_value_b; - end - end - - //TODO: mul update_flags - -endmodule diff --git a/rtl/core/control/mul_fu.sv b/rtl/core/control/mul_fu.sv new file mode 100644 index 0000000..8352435 --- /dev/null +++ b/rtl/core/control/mul_fu.sv @@ -0,0 +1,67 @@ +`include "core/uarch.sv" + +module core_control_mul +( + input logic clk, + rst_n, + + input insn_decode dec, + input logic mul_ready, + input word rd_value_a, + rd_value_b, + + input ctrl_cycle cycle, + next_cycle, + input logic issue, + + output word mul_a, + mul_b, + mul_c_hi, + mul_c_lo, + output reg_num mul_r_add_hi, + mul_r_add_lo, + output logic mul, + mul_add, + mul_long, + mul_start, + mul_signed +); + + word hold_a, hold_b; + + assign {mul_c_hi, mul_c_lo} = {rd_value_a, rd_value_b}; + assign {mul_a, mul_b} = mul_add ? {hold_a, hold_b} : {rd_value_a, rd_value_b}; + + always_ff @(posedge clk or negedge rst_n) + if(!rst_n) begin + mul <= 0; + mul_add <= 0; + mul_long <= 0; + mul_start <= 0; + mul_signed <= 0; + mul_r_add_hi <= {$bits(mul_r_add_hi){1'b0}}; + mul_r_add_lo <= {$bits(mul_r_add_lo){1'b0}}; + + hold_a <= 0; + hold_b <= 0; + end else begin + mul_start <= 0; + + if(next_cycle.issue) begin + mul <= issue && dec.ctrl.mul; + mul_add <= dec.mul.add; + mul_long <= dec.mul.long_mul; + mul_signed <= dec.mul.signed_mul; + mul_r_add_hi <= dec.mul.r_add_hi; + mul_r_add_lo <= dec.mul.r_add_lo; + end else if(next_cycle.mul) + mul_start <= !cycle.mul; + else if(next_cycle.mul_acc_ld) begin + hold_a <= rd_value_a; + hold_b <= rd_value_b; + end + end + + //TODO: mul update_flags + +endmodule diff --git a/rtl/core/control/psr.sv b/rtl/core/control/psr.sv deleted file mode 100644 index 6616bc9..0000000 --- a/rtl/core/control/psr.sv +++ /dev/null @@ -1,81 +0,0 @@ -`include "core/uarch.sv" - -module core_control_psr -( - input logic clk, - rst_n, - - input insn_decode dec, - input word cpsr_rd, - spsr_rd, - alu_b, - input psr_mode exception_mode, - - input ctrl_cycle cycle, - next_cycle, - input logic issue, - - output logic psr, - psr_saved, - psr_write, - psr_wr_flags, - psr_wr_control, - final_psr_write, - final_restore_spsr, - output word psr_wb, - psr_wr -); - - word exception_spsr; - - assign psr_wb = psr_saved ? spsr_rd : cpsr_rd; - - always_comb begin - psr_write = 0; - - if(next_cycle.issue) - psr_write = final_psr_write || final_restore_spsr; - - if(cycle.escalate || cycle.exception) - psr_write = 1; - - if(cycle.escalate) - //TODO: F (FIQ) no cambia siempre - psr_wr = {24'b0, 3'b110, exception_mode}; - else if(cycle.exception) - psr_wr = exception_spsr; - else - psr_wr = final_restore_spsr ? spsr_rd : alu_b; - end - - always_ff @(posedge clk or negedge rst_n) - if(!rst_n) begin - psr <= 0; - psr_saved <= 0; - psr_wr_flags <= 0; - psr_wr_control <= 0; - - exception_spsr <= 0; - final_psr_write <= 0; - final_restore_spsr <= 0; - end else if(next_cycle.issue) begin - psr <= issue && dec.ctrl.psr; - psr_saved <= dec.psr.saved; - psr_wr_flags <= dec.psr.wr_flags; - psr_wr_control <= dec.psr.wr_control; - - final_psr_write <= issue && dec.psr.write; - final_restore_spsr <= issue && dec.psr.restore_spsr; - end else if(next_cycle.escalate) begin - psr_saved <= 0; - psr_wr_flags <= 0; - psr_wr_control <= 1; - exception_spsr <= cpsr_rd; - end else if(next_cycle.exception) begin - psr <= 0; - psr_saved <= 1; - psr_wr_flags <= 1; - end else if(next_cycle.psr) - psr <= 0; - -endmodule diff --git a/rtl/core/control/status.sv b/rtl/core/control/status.sv new file mode 100644 index 0000000..6616bc9 --- /dev/null +++ b/rtl/core/control/status.sv @@ -0,0 +1,81 @@ +`include "core/uarch.sv" + +module core_control_psr +( + input logic clk, + rst_n, + + input insn_decode dec, + input word cpsr_rd, + spsr_rd, + alu_b, + input psr_mode exception_mode, + + input ctrl_cycle cycle, + next_cycle, + input logic issue, + + output logic psr, + psr_saved, + psr_write, + psr_wr_flags, + psr_wr_control, + final_psr_write, + final_restore_spsr, + output word psr_wb, + psr_wr +); + + word exception_spsr; + + assign psr_wb = psr_saved ? spsr_rd : cpsr_rd; + + always_comb begin + psr_write = 0; + + if(next_cycle.issue) + psr_write = final_psr_write || final_restore_spsr; + + if(cycle.escalate || cycle.exception) + psr_write = 1; + + if(cycle.escalate) + //TODO: F (FIQ) no cambia siempre + psr_wr = {24'b0, 3'b110, exception_mode}; + else if(cycle.exception) + psr_wr = exception_spsr; + else + psr_wr = final_restore_spsr ? spsr_rd : alu_b; + end + + always_ff @(posedge clk or negedge rst_n) + if(!rst_n) begin + psr <= 0; + psr_saved <= 0; + psr_wr_flags <= 0; + psr_wr_control <= 0; + + exception_spsr <= 0; + final_psr_write <= 0; + final_restore_spsr <= 0; + end else if(next_cycle.issue) begin + psr <= issue && dec.ctrl.psr; + psr_saved <= dec.psr.saved; + psr_wr_flags <= dec.psr.wr_flags; + psr_wr_control <= dec.psr.wr_control; + + final_psr_write <= issue && dec.psr.write; + final_restore_spsr <= issue && dec.psr.restore_spsr; + end else if(next_cycle.escalate) begin + psr_saved <= 0; + psr_wr_flags <= 0; + psr_wr_control <= 1; + exception_spsr <= cpsr_rd; + end else if(next_cycle.exception) begin + psr <= 0; + psr_saved <= 1; + psr_wr_flags <= 1; + end else if(next_cycle.psr) + psr <= 0; + +endmodule -- cgit v1.2.3