From d9dfa098323bc9ffdc9e976bd4106efc75b2954a Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Tue, 15 Nov 2022 23:18:09 -0600 Subject: Implemente byte-enable signal in stores --- rtl/core/control/control.sv | 1 + rtl/core/control/ldst/ldst.sv | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) (limited to 'rtl/core/control') diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv index adfe9f7..4bff86e 100644 --- a/rtl/core/control/control.sv +++ b/rtl/core/control/control.sv @@ -47,6 +47,7 @@ module core_control output logic[7:0] shifter_shift, output ptr mem_addr, output word mem_data_wr, + output logic[3:0] mem_data_be, output logic mem_start, mem_write, output word mul_a, diff --git a/rtl/core/control/ldst/ldst.sv b/rtl/core/control/ldst/ldst.sv index 02f7b4a..dd5155a 100644 --- a/rtl/core/control/ldst/ldst.sv +++ b/rtl/core/control/ldst/ldst.sv @@ -18,6 +18,7 @@ module core_control_ldst alu_b, output ptr mem_addr, + output logic[3:0] mem_data_be, output word mem_data_wr, mem_offset, output logic mem_start, @@ -57,7 +58,7 @@ module core_control_ldst .read(ldst_read), .shift(ldst_shift), .fault(), //TODO: alignment check - .byteenable(), //TODO + .byteenable(mem_data_be), .* ); -- cgit v1.2.3