From a055bc85bc50897644e7ed62699abff46d818d5f Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Tue, 15 Nov 2022 18:32:55 -0600
Subject: Rewrite duplicate ldst logic as signal ldst_next

---
 rtl/core/control/writeback.sv | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'rtl/core/control/writeback.sv')

diff --git a/rtl/core/control/writeback.sv b/rtl/core/control/writeback.sv
index a85956f..914236c 100644
--- a/rtl/core/control/writeback.sv
+++ b/rtl/core/control/writeback.sv
@@ -23,6 +23,7 @@ module core_control_writeback
 	                   mul_r_add_hi,
 	input  logic       issue,
 	                   pop_valid,
+	                   ldst_next,
 
 	output reg_num     rd,
 	                   final_rd,
@@ -97,7 +98,7 @@ module core_control_writeback
 			if(next_cycle.issue)
 				final_rd <= dec.data.rd;
 			else if(next_cycle.transfer) begin
-				if((!cycle.transfer || mem_ready) && pop_valid)
+				if(ldst_next && pop_valid)
 					final_rd <= popped;
 			end else if(next_cycle.base_writeback)
 				final_rd <= ra;
-- 
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