From 51de19b2caf97e043eb231f2a3cd19d2293ffa2c Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Mon, 2 Oct 2023 18:13:29 -0600 Subject: rtl/core/control: implement exclusive ldst --- rtl/core/control/writeback.sv | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'rtl/core/control/writeback.sv') diff --git a/rtl/core/control/writeback.sv b/rtl/core/control/writeback.sv index a7738fb..50e780d 100644 --- a/rtl/core/control/writeback.sv +++ b/rtl/core/control/writeback.sv @@ -10,6 +10,8 @@ module core_control_writeback input word q_alu, ldst_read, input logic mem_ready, + mem_ex_fail, + mem_ex_lock, mem_write, input word mul_q_hi, mul_q_lo, @@ -62,7 +64,7 @@ module core_control_writeback writeback = 0; if(cycle.transfer) - wr_value = ldst_read; + wr_value = (mem_ex_lock && mem_write) ? {31'd0, mem_ex_fail} : ldst_read; else if(cycle.base_writeback) wr_value = saved_base; else if(cycle.mul || cycle.mul_hi_wb) -- cgit v1.2.3