From d463acba5f9589085afb3dcc4058d82908ff90f2 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Sun, 13 Nov 2022 05:22:23 -0600 Subject: Convert core state machines to Quartus-inferring RTL --- rtl/core/control/stall.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'rtl/core/control/stall.sv') diff --git a/rtl/core/control/stall.sv b/rtl/core/control/stall.sv index c2a6ddd..d590325 100644 --- a/rtl/core/control/stall.sv +++ b/rtl/core/control/stall.sv @@ -24,7 +24,7 @@ module core_control_stall logic pc_rd_hazard, pc_wr_hazard, rn_pc_hazard, snd_pc_hazard, flags_hazard, flags_dependency, updating_flags; - assign stall = next_cycle != ISSUE || next_bubble || halt; + assign stall = !next_cycle.issue || next_bubble || halt; assign halted = halt && !next_bubble; assign next_bubble = pc_rd_hazard || pc_wr_hazard || flags_hazard; @@ -40,6 +40,6 @@ module core_control_stall assign flags_dependency = dec.psr.update_flags || dec.ctrl.conditional; always_ff @(posedge clk or negedge rst_n) - bubble <= !rst_n ? 0 : next_cycle == ISSUE && next_bubble; + bubble <= !rst_n ? 0 : next_cycle.issue && next_bubble; endmodule -- cgit v1.2.3