From b1761b8eac5777c09723bbc8cd31cc05d8ec35ae Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Tue, 6 Dec 2022 15:27:42 -0600 Subject: Implement breakpoints --- rtl/core/control/stall.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'rtl/core/control/stall.sv') diff --git a/rtl/core/control/stall.sv b/rtl/core/control/stall.sv index 085f11e..f42dcf0 100644 --- a/rtl/core/control/stall.sv +++ b/rtl/core/control/stall.sv @@ -24,7 +24,7 @@ module core_control_stall logic pc_rd_hazard, pc_wr_hazard, rn_pc_hazard, snd_pc_hazard, psr_hazard, flags_hazard; assign stall = !next_cycle.issue || next_bubble || halt; - assign halted = halt && !next_bubble; + assign halted = halt && !next_bubble && next_cycle.issue; assign next_bubble = pc_rd_hazard || pc_wr_hazard || flags_hazard || psr_hazard; //FIXME: pc_rd_hazard no debería definirse sin final_writeback? -- cgit v1.2.3